Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.

An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.

Embodiments of the disclosure provide a method for synchronizing a first module and a second module of a logic system design, wherein the first module and the second module operate according to a system clock, the first module includes a plurality of sub-modules, the method comprising: determining, among the plurality of sub-modules, whether a target sub-module generates an event indication; in response to determining that the target sub-module generates the event indication, switching a period of the system clock from a first clock period to a second clock period, wherein the first clock period is less than the second clock period; and running the target sub-module according to the second clock period.

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

Disclosed herein is application specific integrated circuit (ASIC) redesign for security and analysis testing tool, which includes hardware description language code with on-chip security circuitry for detecting and mitigating hardware Trojan horses (HTHs) in an ASIC chip. The testing tool is used between a design stage of the ASIC chip and a synthesis phase of production of the ASIC chip to add test circuitry to the ASIC chip in order to facilitate testing and protecting of the ASIC chip from the HTHs long after production. The test circuitry facilitates search for HTHs, HTH triggering events, and changes made to the ASIC if the HTH has been activated.

A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

Embodiments of the invention relate to a configurable register file for inclusion in ASIC and other integrated circuit designs such as those based on metal configurable standard cell (MCSC) technology. According to certain general aspects, configurable register files provided by the present embodiments improve area, power and routing efficiencies and flexibility over conventional approaches such as hard memory macros and RTL designs. In embodiments, a configurable register file is implemented as a soft macro constructed from metal configurable standard cell (MCSC) base cells. According to certain aspects, unlike a hard memory macro, width and depth are not fixed and can be configured or programmed to any desired dimension or configuration. In some embodiments, a bit array of a configurable register file is comprised of register file bit cells. In other embodiments, a bit array of a configurable register file is comprised of ROM bit cells. In these and other embodiments, a configurable register file is constructed with a bit-line sharing approach that improves the routing and logic resource usage as compared to RTL based memory.