An apparatus for generating a layout for an additive manufacturing of an electric drive for a disc rotor. The disc rotor is adapted for being driven by a magnetic field. The apparatus comprises an input module configured to receive one or more input parameters. The apparatus further comprises a generating module configured to generate, from the one or more input parameters, a layout of a plurality of coil structures, wherein the plurality of coil structures is adapted to generate the magnetic field by an electric current, and a layout of a control structure, wherein the control structure is adapted to connect the plurality of coil structures with a connector for a supply of the electric current, and to distribute the electric current to the plurality of coil structures in order to drive the disc rotor.

Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.

In some embodiments, an apparatus can include a printed circuit board (PCB) that has layers and includes a first portion and a second portion. The first portion can have a data port and a power port. A first layer is associated with data of the first portion of the PCB, and a second layer is associated with power of the first portion of the PCB. The second portion can have a data port and a power port. A third layer is associated with data of the second portion, and a fourth layer is associated with power of the second portion. The first portion or the second portion can have vias defining an electromagnetic interference (EMI) shield. The apparatus can include a power filter and a data filter that can, respectively, isolate power and data of the first portion from the second portion.

The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.

Tools and techniques are described to automate commissioning of physical spaces. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. Controllers also have access to databases of the physical space such that they can check that sensors in the space record the correct information for device activity, and sensors can cross-check each other for consistency. Once a physical space is commissioned, incentives can be sought based on commissioning results.

An assembling method for a multi-core cable having a plurality of electrical insulated wires is designed to connect one-end-portions of the electrical insulated wires to electrode patterns, respectively, of one circuit board, correspondingly connect other-end-portions of the electrical insulated wires to electrode patterns, respectively, of the other circuit board, compute intersection coefficients on one end side and the other of the cable, and iterate interchanging connecting destinations for the one-end-portions of the electrical insulated wires, correspondingly interchanging connecting destinations for the other-end-portions of the electrical insulated wires, and computing the intersection coefficients on the one end side and the other of the cable. The connecting destinations for the electrical insulated wires to the electrode patterns are determined in such a manner that a maximum intersection coefficient denoting either larger one of the respective intersection coefficients of the one end side and the other of the cable is made small.

A board design assistance device includes a design data acquirer to acquire design data for a printed circuit board, a first determiner to determine, based on the design data for the printed circuit board, whether a lengthwise direction of board fiber in the printed circuit board is perpendicular to a longitudinal direction of an electronic component mounted on the printed circuit board, a second determiner to determine, based on the design data for the printed circuit board, whether a wire is routed crosswise from a pad receiving the electronic component mounted on the printed circuit board, and a notifier to provide a notification including error information specifying an electronic component determined to have a longitudinal direction not perpendicular to the lengthwise direction of the board fiber and determined to be connected to a pad from which a wire is not routed crosswise.

Example embodiments describe a computer-implemented method for balancing an electrochemical deposition of metal on a PCB substrate; the method including i) obtaining a layout of the metal on the PCB substrate comprising at least one active area having a circuit layout and a balancing area available for the balancing; ii) dividing the substrate area in a plurality of finite elements; iii) determining active metal fractions from the layout for the respective finite elements; iv) determining metal balancing fractions covering respective finite elements in the balancing area based on the active metal fractions in finite elements in the at least one active area surrounding the respective finite element.

A design support apparatus includes an acquisition unit configured to acquire an electromagnetic wave image in which a captured image obtained by capturing an electronic device and a map obtained by mapping, in a two-dimensional space, a measurement result of an electromagnetic wave radiated from the electronic device are superimposed, and a composition unit configured to cause a display unit to display a CAD drawing representing a shape of the electronic device and the electromagnetic wave image in a superimposed manner such that the CAD drawing and a device image that is an image of the electronic device in the captured image are aligned.