A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

In some embodiments, a computer-implemented method for creating a fabricable segmented design for a physical device is provided. A computing system receives a design specification. The computing system generates a proposed segmented design based on the design specification. The computing system determines two or more loss values based on the proposed segmented design. The computing system combines the two or more loss values to create a combined loss value. The computing system creates an updated design specification using the combined loss value. At least some of the generating, determining, combining, and creating actions are repeated until a fabricable segmented design is generated.

A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including receiving, as input to a trained machine learning model for identifying defect impact with respect to at least one type defect type, data associated with a process related to electronic device manufacturing. The data associated with the process comprises at least one of: an input set of recipe settings for processing a component, a set of desired characteristics to be achieved by processing the component, or a set of constraints specifying an allowable range for each setting of the set of recipe settings. The operations further include obtaining an output by applying the data associated with the process to the trained machine learning model. The output is representative of the defect impact with respect to the at least one defect type.

An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

In at least one example embodiment, a computer system includes a memory storing instructions and at least one processor configured to executed the instructions to cause the computer system to obtain sensor data, the sensor data corresponding to measurements of at least one component of an electric powertrain system of at least one vehicle and generate a first digital twin based on the obtained sensor data, the first generated twin associated with a type of the at least one vehicle.

A security verification system performs security verification of a circuit design. The security verification system simplifies formal security verification of the circuit design by replacing circuit blocks of the circuit with black box circuit blocks. The security verification system instruments the circuit design so that black-boxing can be performed for security verification without changing the security decision over the data paths. The security verification system uses dependence information of the inputs and outputs of the black box to connect inputs of the circuit block with outputs of the circuit block. The black-box circuit block keeps the logic inside the cone of influence of clocks and resets. The system performs security verification of the circuit design by proving a non-interference property of the instrumented circuit design.

Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

This crack estimation device includes: a data determination unit which determines a shape model of a target structure to be inspected, and a crack occurrence plane and an observation plane in the shape model; an estimation data calculation unit which outputs an estimation model for estimating a state of the crack occurrence plane from a state of the observation plane, on the basis of a matrix that associates, with each other, the state of the crack occurrence plane and the state of the observation plane, obtained through numerical analysis of a structural analysis model generated from the shape model; and a crack estimation unit which estimates a state of a crack at the crack occurrence plane on the basis of the estimation model and a measurement value for the target structure actually measured at the observation plane.

Examples described herein provide a computer-implemented method that includes analyzing a first dataset by applying the first dataset to a first model to generate a first result. The method further includes analyzing a second dataset by applying the second dataset to a second model to generate a second result. The method further includes performing validation on the first model and the second model by comparing the first result to the second result. The method further includes, responsive to determining that the first result and the second result match, modifying an operational action of a surface assembly based on at least one of the first result or the second result. The method further includes, responsive to determining that the first result and the second result do not match, updating at least one of the first model or the second model.