A method includes obtaining a target integrated circuit (IC) layout, accessing a repository, identifying a device within the target IC layout by matching an area of the target IC layout to a source pattern, and replacing at least a portion of the area of the target IC layout with a replacement pattern. The repository stores the source pattern for the device and the replacement pattern corresponding to the source pattern.

A simulation method, apparatus, and a storage medium are provided. The simulation method includes: obtaining a pre-built local simulation model of a capacitor array region, wherein the local simulation model is configured to represent first simulation parameters of the capacitor array region; creating a local parameter netlist of a non-capacitor array region, wherein the local parameter netlist includes second simulation parameters of the non-capacitor array region; creating an overall parameter netlist of a peripheral region based on the local simulation model and the local parameter netlist, wherein the overall parameter netlist represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters; and performing simulation on the peripheral region based on the overall parameter netlist.

A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.

A manufacturing system design verification device includes a design information model, a design information input part, a verification logic storage part, and a design information verification part. The design information model is a framework integrating and expressing design information. The design information is inputted to the design information input part. The design information input part converts the design information into an expression described a resource description language with reference to the design information model. The verification logic storage part stores a verification logic including a group of a query described in a query language corresponding to the resource description language and an expected result. The design information verification part includes a query execution engine performing the query on the expression an returning an execution result and a comparison engine comparing the execution result with the expected result and returning a verification result.

A register-transfer level signal mapping construction method and device, wherein the register-transfer level signal mapping construction method comprises: acquiring register-transfer level codes and netlist level codes corresponding to the register-transfer level codes; constructing a circuit according to the register-transfer level codes and the netlist level codes; separating the circuit into a plurality of modules according to syntax of the circuit in a hardware description language; determining a correspondence relationship between the plurality of modules with logic verification methods; acquiring register-transfer level signals of a mapping relationship to be established; and determining netlist level signals corresponding to the register-transfer level codes according to the correspondence relationship between the plurality of modules. A mapping relationship between signals in the register-transfer level signals and signals in the netlist level codes is directly established, which can be implemented easily and done at low cost, and modification of the chip after logic synthesis is convenient.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

There is provided systems and methods to determine a first identifier for first product and manufacturing information (PMI); determine a first computer-aided design (CAD) model comprising a plurality of features; associate a first feature of the plurality of features with the first identifier, wherein the first feature is identified by a second identifier;

associate validation data for the first PMI with the second identifier; detect selection of the first feature in the CAD model; and in response to the detected selection, provide a graphical indication of the validation data.

A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.

A simulation method, simulation device and a readable storage medium are disclosed, in which a correction circuit is added to an equivalent circuit model for a three-terminal circuit employed in a SPICE simulation system. The correction circuit enables simulating behavior of the resistor module, enabling the SPICE simulation system to take in account the body effect. Therefore, simulation results obtained from the simulation model and simulation parameters for the resistor module can better reflect resistor behavior with body effect in an actual circuit, resulting in effectively improved simulation accuracy of the SPICE simulation system and allowing the system to provide more accurate circuit simulation results. Fitting tests can be performed to obtain first-order, second-order and resistor-width-dependent correction coefficients for a body voltage of the resistor module. Thus dependence of resistor behavior on the body voltage can be better predicted, allowing a good reflection of resistor behavior with body effect.