The application discloses a buffer device and a method for controlling data access to an internal memory. The buffer device has a central buffer module coupled to a memory interface to receive a command/address signal via a command/address channel. The central buffer module is configured to detect whether a destination address of the received command/address signal is within a predefined address space, and generate a security read/write signal when the command/address signal is within the predefined address space. The buffer device further has a data buffer module coupled between the memory interface and a memory module to buffer data therebetween. The data buffer module is configured to store reference data, compare the buffered data with the reference data in response to the security read/write signal, and determine whether or not to restrict exchange of the buffered data between the memory module and the memory interface.

A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.

A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.