A semiconductor device capable of efficiently recognizing images utilizing a neural network is provided. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores a parameter of a filter. The shift register group captures image data and outputs part of the image data to the D/A converter while shifting the image data. The D/A converter converts the part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.

A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the first or second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform an arithmetic operation by using the operation values.

A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

The present invention discloses a memristor array, comprising metal wires and memristors; the metal wires are arranged laterally and vertically; a memristor is arranged at the intersection of every two metal wires; the connection/disconnection of the metal wires is judged according to the resistance values of the memristors; and an adder is constituted according to the resistance value states of the memristors. The present invention provides a memristor-CMOS hybrid multiplication core circuit, in which one input of multiplication can be stored in a memristor network, one part of operation is completed in a memory network, the other part of operation is completed through a CMOS circuit, thereby reducing frequent data calls by half, and the power consumption of the CMOS circuit is further reduced by reducing competitive adventure in the operation process, thereby greatly reducing the overall energy consumption.

A semiconductor device that inhibits signal delay and can perform parallel product-sum operations is provided. The semiconductor device includes first to fourth registers, an adder, a multiplier, a selector, and a first memory unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, and an output terminal of the adder is electrically connected to an input terminal of the third register. An output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register, and the first memory unit is electrically connected to a second input terminal of the multiplier. The first memory unit has a function reading out first data corresponding to a context signal input to the first memory unit and inputting the first data to the second input terminal of the multiplier.

Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.

According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.

A method for concurrently performing multiple computations in an associative processing unit (APU) includes having data in two matrices, representing data in two portions of a memory array of the APU, creating a Tartan matrix by computing an outer product between a first bit vector indicating selected rows and a second bit vector indicating selected columns, the Tartan matrix representing data stored in a third portion of the memory array wherein all cells having a value 1 in the Tartan matrix indicate selected cells, concurrently activating all cells of the matrices and storing a result of Boolean operations therebetween in one of the two matrices, wherein a new value is obtained on cells located at a same row and a same column as the selected cells in the Tartan matrix and an original value remains on other cells.

A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.