Embodiments relate to a neural processor circuit that includes a neural engine and a post-processing circuit. The neural engine performs a computational task related to a neural network to generate a processed value. The post-processing circuit includes a random bit generator, an adder circuit and a rounding circuit. The random bit generator generates a random string of bits. The adder circuit adds the random string of bits to a version of the processed value to generate an added value. The rounding circuit truncates the added value to generate an output value of the computational task. The random bit generator may include a linear-feedback shift register (LFSR) that generates random numbers based on a seed. The seed may be derived from a master seed that is specific to a task of the neural network.

A system and method of quickly and efficiently generating a series of random numbers from a source of random numbers in a computing system, Steps includes: loading a data loop (a looped array of stored values with an index) with random data from a source of random data; then repeating the following: reading a value from the data loop in relation to the index; operating on the multi-bit value thereby outputting a derived random number; and moving the index in relation to the looped array. The data loop may be a simple feedback loop which may be a shift register loaded by direct memory access (DMA). The operation may be performed by one or more arithmetic logic units (ALU) which may be fed by one or more data feeds and may perform XOR, Mask Generator, Data MUX, and/or MOD.

Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (V.sub.T) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.

The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations which operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data.

The technical result relates to enabling to select inter-related parameters (performance and required amount of memory) for a particular computing system when implementing a high-dimensional linear transformation.

The use of the present method allows to reduce the amount of consumed memory at a given word size of processors employed.

To this end, based on a specified linear transformation, a modified linear shift register of Galois-type or Fibonacci-type is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.

A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

A method for ascertaining a randomized digital data stream. The method includes ascertaining a first bit stream as a function of an analog input data stream; ascertaining a second randomized bit stream as a function of the first bit stream, the second randomized bit stream being ascertained in a non-periodic temporal sequence; ascertaining a first digital data stream as a function of the second randomized bit stream; ascertaining a second digital data stream including pseudo random numbers; and ascertaining the randomized digital data stream as a function of the first digital data stream and as a function of the second digital data stream.

A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.