Patent classifications
G06F2207/583
Flip-flop based true random number generator (TRNG) structure and compiler for same
A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.
Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address
A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.
Infinite impulse response filters with dithering and methods of operation thereof
A method of filtering includes generating a random value by a random number generator circuit, filtering a first signal by a first filter to form a filtered first signal, dithering the filtered first signal using the random value to form a dithered first signal, filtering a second signal by a second filter to form a filtered second signal, and dithering the filtered second signal using the random value to form a dithered second signal.
Infinite impulse response filters with dithering and methods of operation thereof
An infinite impulse response filter includes a plurality of lower order filter stages and a random number generator circuit. The plurality of lower order filter stages include a first filter stage coupled to a second filter stage. The random number generator circuit includes a first output coupled to the first filter stage and a second output coupled to the second filter stage. The random number generator circuit is configured to generate the same random value at both the first output and the second output. The infinite impulse response filter is an n.sup.th-order filter. The respective order of each of the lower order filter stages is less than n.
INFINITE IMPULSE RESPONSE FILTERS WITH DITHERING AND METHODS OF OPERATION THEREOF
An infinite impulse response filter includes a plurality of lower order filter stages and a random number generator circuit. The plurality of lower order filter stages include a first filter stage coupled to a second filter stage. The random number generator circuit includes a first output coupled to the first filter stage and a second output coupled to the second filter stage. The random number generator circuit is configured to generate the same random value at both the first output and the second output. The infinite impulse response filter is an n.sup.th-order filter. The respective order of each of the lower order filter stages is less than n.
PROCESSOR THAT MITIGATES SIDE CHANNEL ATTACKS BY PROVIDING RANDOM LOAD DATA AS A RESULT OF EXECUTION OF A LOAD OPERATION THAT DOES NOT HAVE PERMISSION TO ACCESS A LOAD ADDRESS
A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.
Apparatus and method
According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of a serial attached small computer system interface (SAS). The external apparatus includes a scrambler. The apparatus includes a descrambler and a controller. The descrambler is configured to descramble frame data scrambled by the scrambler. The controller is configured to, in a case where first frame data is received from the external apparatus, synchronize the descrambler with the scrambler using the first frame data and a first value that is to be scrambled by the scrambler to obtain the first frame data.
INFINITE IMPULSE RESPONSE FILTERS WITH DITHERING AND METHODS OF OPERATION THEREOF
A method of filtering includes generating a random value by a random number generator circuit, filtering a first signal by a first filter to form a filtered first signal, dithering the filtered first signal using the random value to form a dithered first signal, filtering a second signal by a second filter to form a filtered second signal, and dithering the filtered second signal using the random value to form a dithered second signal.
FLIP-FLOP BASED TRUE RANDOM NUMBER GENERATOR (TRNG) STRUCTURE AND COMPILER FOR SAME
A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.
Metastable flip-flop based true random number generator (TRNG) structure and compiler for same
A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.