A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.

An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.

An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

A digital encrypting and decrypting unit (PMEU) that operates according to a Rivest-Shamir-Adleman (RSA) cryptosystem based on Residue Numeral System (RNS) and Chinese Reminder Theorem (CRT). The unit includes two modular exponentiation calculating units (MES-1, MES-2) to process a two residual signals (X mod p; X mod q) to calculate a result of a modular exponentiation by a binary method. The calculating units have inputs (I-k[i], I-SM, I-MM) and outputs (O-k[i], O-SM, O-MM) for signals representing partial results of the modular exponentiation. A modular exponentiation controlling unit (MECU) is connected to the inputs and outputs of the calculating units to control flow of the signals representing the partial results of the modular exponentiation.

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device's consumption of electrical power, or some other property of the target device, that varies during the device's processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack.

A computer-implemented method for enabling elliptic curve arithmetic to be performed using blockchain transactions. A first script of a first blockchain transaction is generated, comprising a modular inversion script configured to obtain a target integer and a modulus value, and output a modular inverse of the target integer. The modular inverse is generated by generating a sequence of squaring values; for each set bit of a reduced modulus value expressed in binary, including the corresponding squaring value of the sequence of squaring values in a result; multiplying together the squaring values of the result to generate a resultant value; and computing a modulus of the resultant value with respect to the modulus value, wherein the modulus of the resultant value is output as the modular inverse, and outputting the first script for inclusion in the first blockchain transaction.