An electronic system such as an imaging system may include processing circuitry and memory circuitry. Data replacement circuitry may be interposed between the processing circuitry and the memory circuitry. In some implementations, the memory circuitry may be a read-only memory, and data replacement circuitry may be used to selectively replace executable firmware instructions stored on the read-only memory. The selective replacement operations may be based on an address that processing circuitry provides to access the memory circuitry. The data replacement circuitry may be implemented separately from the processing circuitry and the memory circuitry and may include a comparator block, registers, and switching circuitry.

An image forming device that executes an image forming program for real-time mechanical control and another program, using a single cache memory for the image forming program and said another program. The image forming device includes: a cache lockdown unit that executes a cache lockdown to lock down a storage area of the cache memory that stores at least a portion of the image forming program necessary for image formation processing; and a print unit that executes the image formation processing while the storage area is locked down.

An electronic device includes a memory, a mode configuration management portion, a panel portion, and a memory management portion. The mode configuration management portion configures a plurality of allocation modes for allocating a plurality of areas to the memory. The panel portion displays a mode selection screen for selecting one of the allocation modes. The memory management portion allocates the plurality of areas to the memory based on the selected one of the allocation modes. The mode configuration management portion manages a plurality of recommended modes. The memory management portion sets sizes of an input portion and an output portion of the respective areas according to the recommended mode selected by the mode configuration management portion.

An electronic system such as an imaging system may include processing circuitry and memory circuitry. Data replacement circuitry may be interposed between the processing circuitry and the memory circuitry. In some implementations, the memory circuitry may be a read-only memory, and data replacement circuitry may be used to selectively replace executable firmware instructions stored on the read-only memory. The selective replacement operations may be based on an address that processing circuitry provides to access the memory circuitry. The data replacement circuitry may be implemented separately from the processing circuitry and the memory circuitry and may include a comparator block, registers, and switching circuitry.

An electronic device includes a memory, a mode configuration management portion, a panel portion, and a memory management portion. The mode configuration management portion configures a plurality of allocation modes for allocating a plurality of areas to the memory. The panel portion displays a mode selection screen for selecting one of the allocation modes. The memory management portion allocates the plurality of areas to the memory based on the selected one of the allocation modes. The mode configuration management portion manages a plurality of recommended modes. The memory management portion sets sizes of an input portion and an output portion of the respective areas according to the recommended mode selected by the mode configuration management portion.

An information processing method to be executed by a processor executing instructions in a memory, the information processing method includes allocating, in a first area of the storage area, an area having a predetermined size to an application, determining whether an processing area to be used when processing of the application is executed in the first area, and upon condition that it is determined that the processing is able to be reserved in the first area, reserving the processing area in the first area as the allocated area having the predetermined size to an application, and upon condition that it is determined that the processing area is not able to be reserved in the first area, trying to reserve the processing area in a second area in the storage area, and performing notification upon condition that the processing is not able to be reserved in the second area.

An image processing system can specify storage locations of necessary functions even when a user-set process flow has been updated. The image processing system includes a setting device and an image processing device. The image processing device includes a storage device and a field programmable gate array (FPGA). The setting device includes a generation part that generates storage location information defining a storage location in the storage part for each of image processing programs to be selected, which have been selected from a library, and a transmission part that transmits the image processing programs to be selected, a process flow defining an execution order of the image processing programs, and the storage location information to the image processing device. The image processing device includes a rewriting part that writes a received image processing program to a storage location of the storage device defined in the storage location information.

Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.

An image processing system can specify storage locations of necessary functions even when a user-set process flow has been updated. The image processing system includes a setting device and an image processing device. The image processing device includes a storage device and a field programmable gate array (FPGA). The setting device includes a generation part that generates storage location information defining a storage location in the storage part for each of image processing programs to be selected, which have been selected from a library, and a transmission part that transmits the image processing programs to be selected, a process flow defining an execution order of the image processing programs, and the storage location information to the image processing device. The image processing device includes a rewriting part that writes a received image processing program to a storage location of the storage device defined in the storage location information.

The present disclosure is directed to memory saving systems and methods for buffer overflow that occurs during image compression. In example embodiments, when an overflow occurs during image compression, the overflow data is written to an allocated designated overflow memory by an overflow handler. This memory can be designed to be rewritten multiple times during the image compression process, and can therefore occupy less memory than would be required in possible alternative solutions that comprise expanding the size of each unit of compression destination memory to account for the worst case compression scenario in each instance. Various embodiments that utilize the designated overflow memory to conserve memory when buffer overflow occurs during image compression are illustrated and described.