An apparatus comprises a memory having a data cache stored therein and a control circuit operably coupled thereto. The control circuit is configured to update that data cache in accordance with a scheduled update time. In the latter regards, by one approach, the control circuit computes selected entries for the data cache prior to the scheduled update time pursuant to a prioritization scheme to provide a substitute data cache. At the scheduled update time, the control circuit switches the substitute data cache for the data cache such that data queries made subsequent to the scheduled update time access the substitute data cache and not the data cache.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

Processing a read request to read metadata from an entry of a metadata page may include: determining whether the metadata page is cached; responsive to determining the metadata page is cached, obtaining the first metadata from the cached metadata page; responsive to determining the metadata page is not cached, determining whether the requested metadata is in a metadata log of metadata changes stored in a volatile memory; and responsive to determining the metadata is the metadata log of metadata changes stored in the volatile memory, obtaining the requested metadata from the metadata log. Processing a write request that overwrites an existing value of a metadata page with an updated value may include: recording a metadata change in the metadata log that indicates to update the metadata page with the updated value; and performing additional processing during destaging that uses the existing value prior to overwriting it with the updated value.

A data management method causes a computer to execute processing including: creating, when a predetermined data processing program performs data processing, based on an access frequency to a data store, high-frequency state item list information obtained by listing high-frequency state items of which the access frequency is high; determining, when state information that includes a value of the high-frequency state item is written to the data store, whether or not the state information corresponds to the high-frequency state item with reference to the high-frequency state item list information; grouping and writing pieces of the state information of a plurality of the high-frequency state item.

A method for constructing a persistent memory index in a non-uniform memory access architecture includes: maintaining partial persistent views in a persistent memory and maintaining a global volatile view in a DRAM; an underlying persistent memory index processing a request in a foreground thread when cold data is accessed; when hot data is accessed, reading a key-value pair for a piece of hot data in the global volatile view in response to a query operation carried in the request, and in response to an insert/update/delete operation carried in the request, updating a local partial persistent view and the global volatile view; and in response to a hotspot migration, a background thread generating new partial persistent views and a new global volatile view, and recycling the partial persistent views and the global volatile view for old hot data into the underlying persistent memory index.

A shared data management system configured to receive frames comprising data from one or more producer devices and to transmit reconstructed frames to one or more consumer devices, a producer device and a consumer device being connected to the shared data management system by way of a communication network using a communication protocol. The shared data management system comprises a memory system having one or more memories. The shared data management system advantageously comprises a central controller configured to store at least some of the data encapsulated in a frame received from a producer device in a target memory area of the memory system, the central controller being configured to compute, for each datum to be stored, the address of the target memory based on an index associated with the datum in the received frame.

Various embodiments of a distributed numeric sequence generation system and method are described. In particular, some embodiments provide high-scale, high-availability, low-cost and low-maintenance numeric sequence generation in a non-Relational Database Management System (“non-RBMS”) system by sacrificing monotonicity. The distributed numeric sequence generation system comprises a plurality of hosts, wherein individual hosts implement a cache for caching a plurality of numeric sequences. A host can access master numeric sequence data at a separate system to obtain values for numeric sequences to store in its cache. A host can receive a request from a client for values of a numeric sequence, and provide to the client the values for the numeric sequence from its cache. Some embodiments of the distributed numeric sequence generation system and method are also equipped to vend recyclable and bounded numeric sequences.

A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

One embodiment describes an automation system including a sensor that determines operational parameters of the automation system; one or more actuators that perform control actions during operation of the automation system; and a control system communicatively coupled to the sensor and the one or more actuators. The control system includes memory that stores the operational parameters; determines occurrence of memory errors in data stored in the memory; determines error parameters that indicate characteristics of the memory errors; determines error-corrected data by correcting the memory errors based at least in part on the error parameters; adaptively adjusts a refresh rate used to refresh stored data in the memory based at least in part on the error parameters; and determines control commands instructing the one or more actuators to perform the control actions by processing the error-corrected data.