A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. To implement PDCCH decoding, a cellular modem can include a pipeline having multiple processing engines, with the processing engines including functional units that execute instructions corresponding to different stages in the PDCCH decoding process. Flow control and data synchronization between instructions can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management.

Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.

A shared data management system configured to receive frames comprising data from one or more producer devices and to transmit reconstructed frames to one or more consumer devices, a producer device and a consumer device being connected to the shared data management system by way of a communication network using a communication protocol. The shared data management system comprises a memory system having one or more memories. The shared data management system advantageously comprises a central controller configured to store at least some of the data encapsulated in a frame received from a producer device in a target memory area of the memory system, the central controller being configured to compute, for each datum to be stored, the address of the target memory based on an index associated with the datum in the received frame.

A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. To implement physical downlink shared channel (PDSCH) decoding, a cellular modem can include a pipeline having multiple processing engines, with the processing engine including functional units that execute instructions corresponding to different stages in the PDSCH decoding process. Flow control and data synchronization between instructions can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management.

A data transmission method is provided. The method includes: a network interface card of a source device obtains a first notification message and a second notification message, wherein the first notification message indicates that a first to-be-processed remote direct memory access (RDMA) request exists in a first queue of the source device, the first queue stores a request of a first service application in the source device, the second notification message indicates that a second to-be-processed RDMA request exists in a second queue of the source device, and the second queue stores a request of a second service application in the source device; and the network interface card determines a processing sequence of the first queue and the second queue based on service levels, and sends the first to-be-processed RDMA request and the second to-be-processed RDMA request to a destination device according to the processing sequence.

A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a n×k addresses, wherein the block comprises a single table, receiving a digital radio broadcast signal at the receiver, and demodulating the digital radio broadcast signal into a plurality of interleaved data units. For at least one series of n×k data units a pointer step size is determined, and for each data unit in the series, an address in the block is calculated based on the pointer step size, and an output data unit is read from the block at the address, such that said output data units represent block deinterleaved data units. An input data unit from the plurality of interleaved data units is then written to the block at the address. Associated systems and computer readable storage media are presented.

A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.

A method for supporting in-flight packet processing is provided. Packet processing devices (microengines) can send a request for packet processing to a packet engine before a packet comes in. The request offers a twofold benefit. First, the microengines add themselves to a work queue to request for processing. Once the packet becomes available, the header portion is automatically provided to the corresponding microengine for packet processing. Only one bus transaction is involved in order for the microengines to start packet processing. Second, the microengines can process packets before the entire packet is written into the memory. This is especially useful for large sized packets because the packets do not have to be written into the memory completely when processed by the microengines.

A user-mode protocol stack-based network isolation method includes: at a bottom-layer network card interface of a user-mode protocol stack, for each network card, adding an isolation space pointer for binding to a network isolation space; when a service application is initialized, configuring a plurality of user-mode protocol stack network isolation spaces with independent protocol stack private tables based on the user-mode protocol stack; for each network card, designating a corresponding user-mode protocol stack network isolation space through the isolation space pointer of each network card; and for service data received from each network card, performing data processing on the service data through protocol stack private tables in a user-mode protocol stack network isolation space corresponding to the network card.

An elastic memory system that may include memory banks, clients that are configured to obtain access requests associated with input addresses; first address converters that are configured to convert the input addresses to intermediate addresses within a linear address space; address scramblers that are configured to convert the intermediate addresses to physical addresses while balancing a load between the memory banks; atomic operation units; an interconnect that is configured to receive modified access requests that are associated with the physical addresses, and send the modified access requests downstream, wherein atomic modified access requests are sent to the atomic operation units; wherein the atomic operations units are configured to execute the atomic modified access requests; wherein the memory banks are configured to respond to the atomic modified access requests and to non-atomic modified access requests.