Volume migration among a set of storage systems synchronously replicating a dataset for a volume, where volume migration includes: initiating a transfer of the volume in dependence upon determining that a performance metric for accessing the volume stored on a first storage system would improve if transferred to a second storage system; and during the transfer of the volume: determining status information for the transfer; intercepting an I/O operation directed to the volume; and directing, in dependence upon the status information, the I/O operation to either the first storage system or the second storage system.

Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.

Disclosed are a method and system for accelerating reading of information of a Field Replace Unit (FRU), a device, and a storage medium. The method includes the following steps: creating, in a storage, a FRU virtual bus; constructing a node data structure based on information of each FRU, and mounting the node data structure to the FRU virtual bus; determining whether an instruction of reading information of a FRU is received; and in response to a receipt of the instruction of reading the information of the FRU, determining a position of the FRU on the FRU virtual bus, and reading the information of the FRU at the position.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

A memory controller includes: a map data storage for storing map data; and a read operation controller for receiving, from a host, a read request and a target logical address corresponding to the read request, acquiring a first physical address mapped to the target logical address, based on the map data, and obtaining data stored at the first physical address. When an uncorrectable error is present in the data stored at the first physical address, the read operation controller acquires a second physical address previously mapped to the target logical address before the first physical address, obtains data stored at the second physical address, and provides the host with the data stored at the second physical address and information representing occurrence of the uncorrectable error.

Validating code that is stored in non-volatile memory. In some instances, code that is written and/or processed by an outside entity that is brought into a local non-volatile memory setting can potentially compromise a given computer system. In order to ensure that this type of code is secure, there are methods to generate interrupt signals that can later be overridden by Otprom code in order to properly validate this outside code.