A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.

A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

A mobile device (100) includes a processing device (140), a random access memory, RAM, (150) and an embedded mass storage device (160). A first interface (IF1) is provided between the processing device (140) and the RAM (150). The first interface (IF1) supports access of the processing device (140) to the RAM (150). The mass storage device (160) includes a controller (170) and a non-volatile flash memory (180). A second interface (IF2) is provided between the controller (170) and the flash memory (180). The second interface (IF2) supports access of the controller (170) to the flash memory (180). A third interface (IF3) is provided between the controller (170) and the processing device (140). The third interface (IF3) supports access of the controller (170) to the RAM (150).

Example implementations disclosed herein include techniques for a ready only bufferpool for use in local nodes of a multi-node computing system. Read only transactions executed by a processor can reference a ready only bufferpool resident in a VRAM on the same node. If the desired data page is in the bufferpool the transaction can immediately read data records from the cached data pages. If the desired data page is not in the bufferpool, then the transaction can cause a copy of a corresponding data page in a secondary memory to be installed in the bufferpool. The bufferpool can include more than one copy of a data page simultaneously to handle and prevent cache line misses. Data page are dropped from the bufferpool based on an incrementing per data page counter.

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2.sup.n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.