G06F2212/281

Detecting shingled overwrite errors

Systems and methods are disclosed for detecting shingled overwrite errors. When a read error is encountered when reading from shingled recording tracks, a processor may determine whether the read error is an error caused by shingled overwriting. The processor may determine whether the read error is caused by shingled overwriting by determining read signal quality of one or more sectors preceding the read error, such as based on a bit error count or bit error ratio (BER), and comparing the read signal quality to a threshold value. The processor may determine that the read error is caused by shingled overwriting when the read signal quality value is lower than the threshold.

Methods for minimizing fragmentation in SSD within a storage system and devices thereof

A method, non-transitory computer readable medium, and device that assists with reducing memory fragmentation in solid state devices includes identifying an allocation area within an address range to write data from a cache. Next, the identified allocation area is determined for including previously stored data. The previously stored data is read from the identified allocation area when it is determined that the identified allocation area comprises previously stored data. Next, both the write data from the cache and the read previously stored data are written back into the identified allocation area sequentially through the address range.

SUPPORTING FAULT INFORMATION DELIVERY

A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

Flushless Transactional Layer

Writing data to storage utilizing a diverged thread for asynchronous write operations is provided. On a first thread, an analysis engine analyzes and identifies changed information to write to storage and an I/O manager copies the writes into buffers and places the buffers into a queue, while on a second thread, a flushless transactional layer (FTL) drive executes the writes to storage. By allowing the analysis to continue and enqueue writes on a first thread while the writes are written to storage on a second thread, the CPU and I/O of the system are utilized in parallel. Accordingly, efficiency of the computing device is improved.

Method and Apparatus for Shared Virtual Memory to Manage Data Coherency in a Heterogeneous Processing System
20180011792 · 2018-01-11 · ·

One embodiment provides for a heterogeneous computing device comprising a first processor coupled with a second processor, wherein one or more of the first or second processor includes graphics processing logic; wherein each of the first processor and the second processor includes first logic to perform virtual to physical memory address translation; and wherein the first logic includes cache coherency state for a block of memory associated with a virtual memory address.

Data updating technology
11698728 · 2023-07-11 · ·

A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends an update data chunk obtained from to-be-written data to a corresponding storage node. The storage node does not directly update, based on the received update data chunk, a data block stored in a storage device of the storage node, but store the update data chunk into a non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node for backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

MAGNETIC DISK DEVICE
20230093769 · 2023-03-23 ·

According to one embodiment, a magnetic disk device includes a first magnetic disk comprising a first recording surface accessed by using a first actuator system and second magnetic disk comprising a second recording surface accessed by using a second actuator system. The first recording surface includes a first area to which a logical address is mapped and a cache area. The second recording surface includes a second area to which a logical address is mapped and a cache area. When receiving first data whose final write destination is the first recording surface from a host, the controller writes the first data to a buffer memory. When the first event occurs, after the first data has been written to the buffer memory and before the first data has been written to the final write destination, the controller writes the first data in the buffer memory to the second area.

System and Method for Reducing CPU Load and Latency for Scheduled Snapshots using Pre-Allocated Extents
20230126573 · 2023-04-27 ·

A method, computer program product, and computer system for identifying, by a computing device, a number of extents needed for a create snapshot operation to create a snapshot. The number of extents may be added to an in-memory cache. The number of extents needed for the create snapshot operation may be allocated from the in-memory cache to execute the create snapshot operation. Freed extents may be added to the in-memory cache based upon, at least in part, executing a delete snapshot operation to delete the snapshot.

Cache program operation of three-dimensional memory device with static random-access memory

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

Provisioning virtual machines with a single identity and cache virtual disk

A virtual disk is provided to a computing environment. The virtual disk includes identity information to enable identification of a virtual machine within the computing environment. A size of the virtual disk is increased within the computing environment to enable the virtual disk to act as a storage for the identity information and as a cache of other system data to operate the virtual machine. The virtual machine is booted within the computing environment. The virtual machine is configured to at least access the virtual disk that includes both identity information and caches other system data to operate the virtual machine. Related apparatus, systems, techniques and articles are also described.