A memory device with non-volatile memory and persistent predictive prefetching provides highspeed storage to a computer system. The memory device uses a non-volatile memory to store data and a volatile memory to cache the data from the non-volatile memory. The computer system sends access requests to obtain data in the non-volatile memory. A prediction engine in the memory device receives the access requests. The prediction engine compute access histories based on the access requests and stores them in an access history table. The prediction engine computes prediction of non-volatile memory addresses that will be accessed in the future based on the stored access history table. The prediction engine causes to store the data from the predicted addresses of the non-volatile memory in the volatile memory. The memory device stores the prediction in the non-volatile memory so the past predictions can be used after restarting the computer system.

Systems, apparatuses, and methods provide for a memory controller to manage a tiered memory including a zoned namespace drive memory capacity tier. For example, a memory controller includes logic to translate a standard zoned namespace drive address associated with a user write to a tiered memory address write. The tiered memory address write is associated with the tiered memory including the persistent memory cache tier and the zoned namespace drive memory capacity tier. A plurality of tiered memory address writes are collected, where the plurality of tiered memory address writes include the tiered memory address write and other tiered memory address writes in the persistent memory cache tier. The collected plurality of tiered memory address writes are transferred from the persistent memory cache tier to the zoned namespace drive memory capacity tier, via an append-type zoned namespace drive write command.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

A method for block addressing is provided. The method includes moving content of a data block referenced by a logical block address (LBA) from a first physical block corresponding to a first physical block address (PBA) to a second physical block corresponding to a second PBA, wherein prior to the moving a logical map maps the LBA to a middle block address (MBA) and a middle map maps the MBA to the first PBA and in response to the moving, updating the middle map to map the MBA to the second PBA instead of the first PBA.

A Memory Device (MD) for storing temporary data designated for volatile storage by a processor and persistent data designated for non-volatile storage by the processor. An address is associated with a first location in a volatile memory array and with a second location in a Non-Volatile Memory (NVM) array of the MD. Data is written in the first location, and flushed from the first location to the second location. A refresh rate for the first location is reduced after flushing the data from the first location until after data is written again to the first location. In another aspect, a processor designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.

A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

Aspects of the present disclosure relate to asynchronous memory management. In embodiments, an input/output (IO) workload is received at a storage array. Further, one or more read-miss events corresponding to the IO workload are identified. Additionally, at least one of the storage array's cache slots is bound to a track identifier (TID) corresponding to the read-miss events based on one or more of the read-miss events' two-dimensional metrics.

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.

The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.