A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

The present technology relates to an electronic device. A memory controller that increases a hit ratio of a cache memory includes a memory buffer configured to store command data corresponding to a request received from a host, and a cache memory configured to cache the command data. The cache memory stores the command data by allocating cache lines based on a component that outputs the command data and a flag included in the command data.

Systems and methods are described for transforming a data set within a data source into a series of task calls to an on-demand code execution environment or other distributed code execution environment. Such environments utilize pre-initialized virtual machine instances to enable execution of user-specified code in a rapid manner, without delays typically caused by initialization of the virtual machine instances, and are often used to process data in near-real time, as it is created. However, limitations in computing resources may inhibit a user from utilizing an on-demand code execution environment to simultaneously process a large, existing data set. The present application provides a task generation system that can iteratively retrieve data items from an existing data set and generate corresponding task calls to the on-demand computing environment, while ensuring that at least one task call for each data item within the existing data set is made.

Data processing apparatuses, methods of data processing, instructions, and simulator computer programs for providing a corresponding instruction execution environment are disclosed. Decode circuitry is responsive to an instance of a predetermined instruction type to cause issue circuitry to issue at least one subsequent instruction for execution to one of first and second instruction execution circuitry which support decoupled access-execute instruction execution. The predetermined instruction type is thus a steering instruction for at least one subsequent instruction and the programmer is provided with a mechanism for determining which program instructions are treated as access instructions and which are treated as execute instructions.

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

A system includes a processor and memory including one or more memory region groups, each including a plurality of distinct memory regions. In embodiments, each memory region of a particular memory region group has a same set of memory attributes and is associated with a same attribute group identifier (AGI). In response to an access request to a memory location of a memory region within the particular memory region group, the AGI may be used to identify the set of memory attributes to be applied when executing the access request. In response to a request to change one or more memory attributes of the particular memory region group, update of a single entry changes the memory attributes for all memory regions of the particular memory region group, without accessing individual metadata of each memory region. The update can be accomplished atomically and substantially simultaneously.

Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.

A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.