Patent classifications
G06F2212/502
REDUCING IDLE RESOURCE USAGE
A method, computer program product, and system for reallocating resources of an idle application or program includes a computer for running an application or a program and starting a predetermined time interval. The computer increases a number counter for each event triggered during the predetermined time interval, and the event is a predetermined trigger that is activated during the running of the application or program. The method and system includes comparing a total number of events that occur during the predetermined time interval to a threshold value. The total number of events is the value of the number counter at the end of the predetermined interval. In response to determining, by the computer, the total number of events being below the threshold value, releasing resources allocated to the program by activating, using the computer, either: i) a garbage collector application, or ii) a resource release application.
Methods and systems for a stripe mode cache pool
N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.
Memory pooling between selected memory resources
Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.
MEMORY POOLING BETWEEN SELECTED MEMORY RESOURCES
Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.
Low-latency direct cloud access with file system hierarchies and semantics
Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.
SYSTEMS AND METHODS FOR ADAPTIVE HYBRID HARDWARE PRE-FETCH
An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.
MEMORY MODULE, SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF MEMORY MODULE
A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.
CACHE MEMORY ARCHITECTURE AND MANAGEMENT
Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.
CACHE MEMORY ARCHITECTURE AND MANAGEMENT
Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.
Optimization of data access and communication in memory systems
A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores the data items at the memory locations separated by different memory regions according to different contexts.