The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.

Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.

Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A method for stream-processing biomedical data includes receiving, by a file system on a computing device, a first request for access to at least a first portion of a file stored on a remotely located storage device. The method includes receiving, by the file system, a second request for access to at least a second portion of the file. The method includes determining, by a pre-fetching component executing on the computing device, whether the first request and the second request are associated with a sequential read operation. The method includes automatically retrieving, by the pre-fetching component, a third portion of the requested file, before receiving a third request for access to least the third portion of the file, based on a determination that the first request and the second request are associated with the sequential read operation.

A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

Described herein is a graphics processing unit (GPU) comprising a first processing cluster to perform parallel processing operations, the parallel processing operations including a ray tracing operation and a matrix multiply operation; and a second processing cluster coupled to the first processing cluster, wherein the first processing cluster includes a floating-point unit to perform floating point operations, the floating-point unit is configured to process an instruction using a bfloat16 (BF16) format with a multiplier to multiply second and third source operands while an accumulator adds a first source operand with output from the multiplier.

The present disclosure discloses a control device of data storage system, including a host interface, a peer interface, a storage unit interface, a processor and a local data management module. The host interface is connected and communicated with a storage server for data interaction with the storage server. The peer interface is configured for data communication connection with a storage unit of an adjacent control device in the data storage system. The storage unit interface is configured to connect a storage unit. The local data management module is configured for local data management of the data in the storage unit according to the data management instruction via the processor. The host interface is configured to send result data of local data management to the storage server.

Systems and methods for determining an access pattern in a computing system. Accesses to a file may contain random accesses and sequential accesses. The file may be divided into multiple regions and the accesses to each region are tracked. The access pattern for each region can then be determined independently of the access patterns of other regions of the file.