Systems, devices, apparatuses, components, methods, and techniques for predicting user and media-playback device states are provided. Systems, devices, apparatuses, components, methods, and techniques for representing cached, user-selected, and streaming content are also provided.

Techniques to shared system memory across nodes in a system. Circuitry is arranged to provide a mechanism to share a memory region of a memory maintained at a first host CPU at a first node across multiple other host CPUs at multiple other nodes using various links and protocols described in one or more revisions of the Compute Express Link (CXL) specification.

A data management method causes a computer to execute processing including: creating, when a predetermined data processing program performs data processing, based on an access frequency to a data store, high-frequency state item list information obtained by listing high-frequency state items of which the access frequency is high; determining, when state information that includes a value of the high-frequency state item is written to the data store, whether or not the state information corresponds to the high-frequency state item with reference to the high-frequency state item list information; grouping and writing pieces of the state information of a plurality of the high-frequency state item.

Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to issue an unaligned transaction, determine that there is a transfer failure indication for the unaligned transaction, and retry the unaligned transaction with either a different alignment or a different transfer size. The different alignment or the different transfer size is used for another unaligned transaction from a same address range upon successful retry of the unaligned transaction.

A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

Coordinating dynamic power scaling of agents based on power correlations of agent instructions is disclosed. A global power controller determines a first local power quantifier of a first agent executing an agent instruction of a task of a workload. The global power controller stores a correlation between the first agent executing the agent instruction and a second local power quantifier corresponding to a second agent. The global power controller subsequently determines that the first agent is executing or will execute the agent instruction. The global power controller accesses the correlation associated with the first agent executing the agent instruction and sends to the second agent a proposed power level based on the correlation.

A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.