Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

A method of performing a garbage collection operation on a source block includes: performing a plurality of partial page clean operations during a series of host write operations. Each partial clean operation includes: performing a validity check process within a partitioned searching range of the source block to obtain valid page information; and performing a page clean process according to the valid page information and a target clean page number to read valid pages indicated by the valid page information.

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.

The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.

An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.

A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

A method for managing a memory apparatus comprising a plurality of NV memory elements is disclosed. The method includes providing a physical block of each NV memory element with a local page address linking table by obtaining a first host address and first data from a first host command, and obtaining a second host address and second data from a second host command; linking the first host address to a first page of the physical block; and linking the second host address to a second page of the physical block. A global page address linking table is built by reading the local page address linking tables and stored in a volatile memory. For the local page address linking table, a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.