Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect whether a threshold number of interrupt requests have been received by the interrupt controller for an external event group. The interrupt controller also includes holding circuitry configured to hold release of the interrupt and to release the held interrupts after the external event has been received by the interrupt controller.

Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect whether a threshold number of interrupt requests have been received by the interrupt controller for a membership group. The interrupt controller also includes holding circuitry configured to hold release of the interrupt until the threshold number of interrupt requests has been received by the interrupt controller.

Systems or methods of the present disclosure may provide for interrupt clustering using a processor and/or system on a chip. An interrupt controller includes an input terminal configured to receive an interrupt request and an output terminal configured to output an interrupt based on the interrupt request. The interrupt controller also includes detection circuitry configured to detect that an interrupt request of the plurality of interrupt requests has been received and to start a counter for a timing group based on receiving the interrupt request. The interrupt controller also includes holding circuitry configured to hold release of an interrupt of the plurality of interrupts corresponding to the interrupt request until the counter reaches a threshold value.

A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

A troubleshooting method implemented by a processor device is provided, comprising determining, according to collected information of correctable errors, that a correctable error storm has occurred, disabling a system management interrupt (SMI) of generation modules of correctable errors in a correctable error set, wherein the correctable error set comprises correctable errors related to the correctable error storm, sending SMI-disabled notification information to a baseboard management controller (BMC), receiving enable-SMI notification information that is sent by the BMC after a predetermined time elapses after the SMI-disabled notification information has been received, and enabling the disabled SMI of the generation modules of the correctable errors according to the enable-SMI notification information.

A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

A troubleshooting method implemented by a processor device is provided, comprising determining, according to collected information of correctable errors, that a correctable error storm has occurred, disabling a system management interrupt (SMI) of generation modules of correctable errors in a correctable error set, wherein the correctable error set comprises correctable errors related to the correctable error storm, sending SMI-disabled notification information to a baseboard management controller (BMC), receiving enable-SMI notification information that is sent by the BMC after a predetermined time elapses after the SMI-disabled notification information has been received, and enabling the disabled SMI of the generation modules of the correctable errors according to the enable-SMI notification information.