An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

A timing control method and system applied on the network simulator platform are disclosed. When at least one subprocess calls a system call to enter a blocking I/O, a marking operation is performed, the kernel issues a first notification event to a network simulator, to request the network simulator to pause until the subprocess leaves from the blocking I/O. when the kernel detects that the subprocess leaves from the blocking I/O already, the kernel issues a second notification event to the network simulator, so that the network simulator continues to simulate. The present invention can control the subprocess to not continuously occupy resource, and first and second notification events can prevent a simulator timer from continuously running during the subprocess execution period, to cause an abnormal timing of a simulation result.

An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

A USB-C connection line and a USB-C connection line signal judgement method thereof are disclosed. The USB-C connection line can be connected between a first electronic device and a second electronic device. The USB-C connection line includes a receiver detector, a first signal detector, a second signal detector, and a controller. The receiver detector is used to detect whether a receiver signal is received; the receiver signal means that the first electronic device or the second electronic device is connected to a first port or a second port. The first signal detector and the second signal detector are used to detect whether an input signal is transmitted from the first electronic device or the second electronic device. The controller is used to determine whether any one of the input signal or the receiver signal is received so as to execute a startup procedure.

A USB-C connection line and a USB-C connection line signal judgement method thereof are disclosed. The USB-C connection line can be connected between a first electronic device and a second electronic device. The USB-C connection line includes a receiver detector, a first signal detector, a second signal detector, and a controller. The receiver detector is used to detect whether a receiver signal is received; the receiver signal means that the first electronic device or the second electronic device is connected to a first port or a second port. The first signal detector and the second signal detector are used to detect whether an input signal is transmitted from the first electronic device or the second electronic device. The controller is used to determine whether any one of the input signal or the receiver signal is received so as to execute a startup procedure.

A timing control method and system applied on the network simulator platform are disclosed. When at least one subprocess calls a system call to enter a blocking I/O, a marking operation is performed, the kernel issues a first notification event to a network simulator, to request the network simulator to pause until the subprocess leaves from the blocking I/O. when the kernel detects that the subprocess leaves from the blocking I/O already, the kernel issues a second notification event to the network simulator, so that the network simulator continues to simulate. The present invention can control the subprocess to not continuously occupy resource, and first and second notification events can prevent a simulator timer from continuously running during the subprocess execution period, to cause an abnormal timing of a simulation result.

Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. However, excessive interrupts become a burden to the host device. In that regard, the memory device includes a dynamic and adaptive interrupt coalescing methodology according to one or more parameters including: the completion queue; the commands; the queue depth; latency; and memory device firmware settings. In this way, the memory device may reduce the number of interrupts while still notifying the host device in a timely manner.

An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.

A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. However, excessive interrupts become a burden to the host device. In that regard, the memory device includes a dynamic and adaptive interrupt coalescing methodology according to one or more parameters including: the completion queue; the commands; the queue depth; latency; and memory device firmware settings. In this way, the memory device may reduce the number of interrupts while still notifying the host device in a timely manner.