A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.

A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

A storage device retrieves commands from a command queue of a host and monitors depth of the command queue. Commands are executed from the command queue and outcomes of the commands are written to a completion queue of the host. Interrupts for the completed commands are coalesced until an aggregation threshold or aggregation delay are met. Coalescing is disabled and interrupts generated upon completion of commands when depth of the command queue is below a threshold.

A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.

A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.

An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction. Each output interface has queue storage comprising a plurality of queue entries, where each queue entry is allocated to a transaction received by the output interface and is used to store interrupt identifying information provided by a data portion of the transaction. The queue storage is arranged to maintain duplication tracking information to identify when both the original transaction and its associated duplicate transaction have been received by the output interface. Each output interface inhibits issuing an output signal that would cause an interrupt request for the original transaction to be sent to the associated processing device, until the duplication tracking information identifies that both the original transaction and the associated duplicate transaction have been received by that output interface. This provides an efficient functional safety compliant design for an interrupt controller.

The disclosure is related to a circuitry system and a method for processing interrupt priority. The circuitry system is such as a system-on-chip that operates the method. The high-priority interrupt is configured to be always on and prohibited from accessing a critical section. When a high-priority interrupt occurs as a processor of the system is in operation, the processor sets a low-priority interrupt to access the critical section where the high-priority interrupt accessed previously. When the low-priority interrupt is terminated, the processor determines whether or not to wake up the unfinished task that is previously set for the high-priority interrupt. The processor continues processing the task since the task has not been finished. The circuity system can therefore retain the characteristics of all disabled interrupts and also maintain an instantaneity for the important tasks of the system.

A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.