A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

In a method for SR-IOV Virtual Functions Sharing on Multi-Hosts, implemented in a management system, one or more fake devices are simulated in one or more hosts with each fake device corresponding to one of a plurality of SR-IOV virtual functions. Each of one or more configuration spaces is redirected from each SR-IOV virtual function to each fake device, respectively. Each of configuration space requests is redirected from a corresponding fake device to a corresponding SR-IOV virtual function when the configuration space request is received. And each of memory access operations is redirected from the corresponding SR-IOV virtual function to a mapped memory on a corresponding host with the corresponding fake device, and each of interrupts generated by one or more SR-IOV virtual machines is redirected to the corresponding fake device.

An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

According to embodiments, in an interrupt request processing device including one or more peripheral devices, one or more processor interfaces, and one or more processors, when an interrupt request (IRQ) is generated, the peripheral device generates a packet and transmit the packet to the processor interface via an on-chip network, the processor interface receives and decodes the packet to transmit the IRQ signal to the processor, and receives an interrupt vector generated from the processor to transmit an initial instruction corresponding to an activated interrupt request may transmit to the processor, and the processor outputs the interrupt vector in response to the IRQ signal and executes a corresponding interrupt service routine (ISR).

According to embodiments, in an interrupt request processing device including one or more peripheral devices, one or more processor interfaces, and one or more processors, when an interrupt request (IRQ) is generated, the peripheral device generates a packet and transmit the packet to the processor interface via an on-chip network, the processor interface receives and decodes the packet to transmit the IRQ signal to the processor, and receives an interrupt vector generated from the processor to transmit an initial instruction corresponding to an activated interrupt request may transmit to the processor, and the processor outputs the interrupt vector in response to the IRQ signal and executes a corresponding interrupt service routine (ISR).

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

A service request interrupt router having an interrupt controller mapped to an Interrupt Service Provider (ISP) having virtual ISPs; Service Request Nodes (SRNs) configured to convert respective interrupt signals to corresponding service requests, wherein each of the SRNs is configured to direct its service request to one of the virtual ISPs; and an arbitrator configured to arbitrate among the virtual ISPs in a time-multiplexed sequence or round-robin manner, and for each of the virtual ISPs, to arbitrate which of the service requests directed thereto has a highest priority.

A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

A service request interrupt router having an interrupt controller mapped to an Interrupt Service Provider (ISP) having virtual ISPs; Service Request Nodes (SRNs) configured to convert respective interrupt signals to corresponding service requests, wherein each of the SRNs is configured to direct its service request to one of the virtual ISPs; and an arbitrator configured to arbitrate among the virtual ISPs in a time-sliced manner, and for each of the virtual ISPs, to arbitrate which of the service requests directed thereto has a highest priority.

An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.