An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Methods and apparatus for efficient data transmit and receive operations using polling of memory queues associated with interconnect fabric interface. In one embodiment, Non-Transparent Bridge (NTB) technology used to transact the data transmit/receive operations and a hardware accelerator card used implement a notification mechanism in order to optimize of receive queue polling are disclosed. The accelerator card comprises a notification address configured to signal the presence of data, and a notification acknowledgement region configured to store flags associated with memory receive queues. In one implementation, the interconnect fabric is based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters.

Methods and apparatus for efficient data transmit and receive operations using polling of memory queues associated with interconnect fabric interface. In one embodiment, Non-Transparent Bridge (NTB) technology used to transact the data transmit/receive operations and a hardware accelerator card used implement a notification mechanism in order to optimize of receive queue polling are disclosed. The accelerator card comprises a notification address configured to signal the presence of data, and a notification acknowledgement region configured to store flags associated with memory receive queues. In one implementation, the interconnect fabric is based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters.

A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

An emulator is configured with a circuit design model for a circuit design comprising a processor and is running with an operating system. Data are transferred from a computer to a memory in the emulator through a design-independent interface or a transaction-level interface. A software program is then activated in the emulator to enable the data to be accessed by the operating system without rebooting the emulator.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.

To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.