A dry-type transformer, comprises a magnetic core, at least one high voltage (HV) winding, and at least one low voltage (LV) winding inductively coupled to the magnetic core. The transformer is made by determining a shape of an electric field that is generated, 3D printing a dielectric structure shaped to conform to the determined shape of the electric field, and mounting the dielectric structure between the HV and LV windings. A dielectric barrier arrangement for electrically isolating a coil of a transformer assembly from a further coil of the transformer assembly or from a core of the transformer assembly comprises a first dielectric structure having a first cylindrical dielectric structure extending along a longitudinal axis (L).

An apparatus for generating a layout for an additive manufacturing of an electric drive for a disc rotor. The disc rotor is adapted for being driven by a magnetic field. The apparatus comprises an input module configured to receive one or more input parameters. The apparatus further comprises a generating module configured to generate, from the one or more input parameters, a layout of a plurality of coil structures, wherein the plurality of coil structures is adapted to generate the magnetic field by an electric current, and a layout of a control structure, wherein the control structure is adapted to connect the plurality of coil structures with a connector for a supply of the electric current, and to distribute the electric current to the plurality of coil structures in order to drive the disc rotor.

An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

The present invention discloses a system and method for simulating radio frequency (RF) signal propagation through a plurality of mediums using a plurality of configurable digital representations of building information model in two dimensional (2D) or augmented reality (AR) or virtual reality (VR) environments. The system comprising: a client interface, a processor and a memory. The processor comprising a building information model (BIM) generation unit, RF equipment conversion unit and a RF propagation prediction unit. The BIM generation unit is configured to translate 2D graphics into BIM data-sets, by reference to administrator input, to act as one or more parameters to control a generation of 2D or AR or VR environments. The RF equipment conversion unit is configured to transform adjunct data related to a physical configuration of one or more RF equipment into data models. The RF propagation prediction unit is configured to utilize the one or more parameters and the transformed data related to the physical configuration of the one or more RF equipment for simulating the RF signal propagation pattern predictions through the plurality of mediums.

A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.