A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

Aspects of the invention include a computer-implemented method of hierarchical large block synthesis (HLBS). At least a partial ring is created around an HLBS structure. The partial ring includes at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes. Certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic are identified. Decoupling capacitors of the relatively large sizes are disposed in the certain areas. A remainder of the areas of the HLBS structure are filled with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

Aspects of the invention include a computer-implemented method of hierarchical large block synthesis (HLBS). At least a partial ring is created around an HLBS structure. The partial ring includes at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes. Certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic are identified. Decoupling capacitors of the relatively large sizes are disposed in the certain areas. A remainder of the areas of the HLBS structure are filled with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

An apparatus for generating a layout for an additive manufacturing of an electric drive for a disc rotor. The disc rotor is adapted for being driven by a magnetic field. The apparatus comprises an input module configured to receive one or more input parameters. The apparatus further comprises a generating module configured to generate, from the one or more input parameters, a layout of a plurality of coil structures, wherein the plurality of coil structures is adapted to generate the magnetic field by an electric current, and a layout of a control structure, wherein the control structure is adapted to connect the plurality of coil structures with a connector for a supply of the electric current, and to distribute the electric current to the plurality of coil structures in order to drive the disc rotor.

An apparatus for generating a layout for an additive manufacturing of an electric drive for a disc rotor. The disc rotor is adapted for being driven by a magnetic field. The apparatus comprises an input module configured to receive one or more input parameters. The apparatus further comprises a generating module configured to generate, from the one or more input parameters, a layout of a plurality of coil structures, wherein the plurality of coil structures is adapted to generate the magnetic field by an electric current, and a layout of a control structure, wherein the control structure is adapted to connect the plurality of coil structures with a connector for a supply of the electric current, and to distribute the electric current to the plurality of coil structures in order to drive the disc rotor.