The present invention relates to a preparation method for a dry film solder resist (DFSR) capable of forming the DFSR having fine unevenness on a surface by a more simplified method, and a film laminate used therein. The preparation method for a dry film solder resist includes forming a predetermined photo-curable and heat-curable resin composition on a transparent carrier film having a surface on which a fine unevenness having an average roughness (Ra) of 200 nm to 2 μm is formed; laminating the resin composition on a substrate to form a laminated structure in which the substrate, the resin composition, and the transparent carrier film are sequentially formed; exposing the resin composition and delaminating the transparent carrier film; and alkaline-developing the resin composition in a non-exposure part and performing heat-curing.

A method and system for generating a high-order pseudo-random electromagnetic exploration signal. The method includes: constructing two or more basic unit signals according to an exploration requirement, where the basic unit signals are stairstep signals obtained by superposing a plurality of in-phase periodic square wave signals, and a frequency ratio between adjacent ones of the plurality of periodic square wave signals is 2; and superposing the two or more basic unit signals to obtain superposed stairstep signals, and correcting amplitudes to be consistent with amplitudes of the periodic square wave signals, to obtain high-order 2.sup.n sequence pseudo-random signals. The 2.sup.n sequence stairstep signals of different orders can be constructed within a limited frequency interval, improving the resolution during electromagnetic exploration.

A method and system for generating a high-order pseudo-random electromagnetic exploration signal. The method includes: constructing two or more basic unit signals according to an exploration requirement, where the basic unit signals are stairstep signals obtained by superposing a plurality of in-phase periodic square wave signals, and a frequency ratio between adjacent ones of the plurality of periodic square wave signals is 2; and superposing the two or more basic unit signals to obtain superposed stairstep signals, and correcting amplitudes to be consistent with amplitudes of the periodic square wave signals, to obtain high-order 2.sup.n sequence pseudo-random signals. The 2.sup.n sequence stairstep signals of different orders can be constructed within a limited frequency interval, improving the resolution during electromagnetic exploration.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

In order to provide smaller, faster and less error-prone circuits for sorting possibly metastable inputs, a novel sorting circuit is provided. According to the invention, the circuit is metastability-containing.

An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.

The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

The disclosure is directed to a system, device and method for data storage on implantable magnetizable fabric. The system includes implantable magnetizable fabric coupled to a graft segment of a prosthesis for being delivered into a body of a subject. The system includes information written on the implantable magnetizable fabric. The system further includes a magnetic detection device capable of, after the prosthesis is delivered into the body of the subject, detecting the implantable magnetizable fabric and accessing at least a portion of the information.

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.