A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

A neural network processor for performing a neural network operation may include a memory storing computer-readable instructions, and kernel intermediate data, the kernel intermediate data including a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and at least one processor to execute the computer-readable instructions to perform a convolution operation by selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on an input feature map.

A tool for an approach and mechanism for calculating and configuring memory mapping of trend log objects in a system, such as an HVAC. It may incorporate determining available memory of a controller for trending a unit of equipment of a system. A calculation of available records may be made for configuring and using a trend. The calculation may be made in view of the controller memory and parameters including buffer size, log interval and retention time. A change in parameters may cause a recalculation of available records. The “available record” terms may be regarded as being in a user-understandable format. The format may be intuitive. Anomalies of trends of equipment may lead to spotting issues of the equipment.

A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

An accelerating device includes a signal detector that converts a first input signal and a second input signal into a first converted input signal and a second converted input signal, respectively, and that generates a final zero-value flag signal, a first one-value flag signal, and a second one-value flag signal. The accelerating device further includes a processing element (PE) that processes the first converted input signal and the second converted input signal based on the final zero-value flag signal, the first one-value flag signal, and the second one-value flag signal and that skips a first arithmetic operation and a second arithmetic operation when the final zero-value flag signal has a first value. The first value of the final zero-value flag signal indicates that the first input signal, or the second input signal, or both have a value of 0.

An accelerating device includes a signal detector that converts a first input signal and a second input signal into a first converted input signal and a second converted input signal, respectively, and that generates a final zero-value flag signal, a first one-value flag signal, and a second one-value flag signal. The accelerating device further includes a processing element (PE) that processes the first converted input signal and the second converted input signal based on the final zero-value flag signal, the first one-value flag signal, and the second one-value flag signal and that skips a first arithmetic operation and a second arithmetic operation when the final zero-value flag signal has a first value. The first value of the final zero-value flag signal indicates that the first input signal, or the second input signal, or both have a value of 0.

A neural network processor for performing a neural network operation may include a memory storing computer-readable instructions, and kernel intermediate data, the kernel intermediate data including a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and at least one processor to execute the computer-readable instructions to perform a convolution operation by selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on an input feature map.

An approach and mechanism for improving reliability, performance and on time execution of critical operations of a system, such as an HVAC. A controller may have two or more processing cores. One core may be dedicated to execution of critical operations of a system. Another core may be dedicated to less- or non-critical operations of the system. For instance, if there are delays relative to the less- or non-critical operations, these delays may be ineffective relative to the processing of critical operations.

A tool for an approach and mechanism for calculating and configuring memory mapping of trend log objects in a system, such as an HVAC. It may incorporate determining available memory of a controller for trending a unit of equipment of a system. A calculation of available records may be made for configuring and using a trend. The calculation may be made in view of the controller memory and parameters including buffer size, log interval and retention time. A change in parameters may cause a recalculation of available records. The available record terms may be regarded as being in a user-understandable format. The format may be intuitive. Anomalies of trends of equipment may lead to spotting issues of the equipment.

Provided are a spin logic device based on a magnetic tunnel junction and an electronic apparatus comprising the same. According to an embodiment, the spin logic device may comprise: a current wiring; a magnetic tunnel junction, which comprises a free magnetic layer, a fixed magnetic layer, and a potential barrier layer located therebetween, which are stacked on the current wiring; and a current source for providing an input current to the current wiring, wherein the input current comprises a first, a second, and a third in-plane currents, directions of which are different from a direction of a magnetization axis of the free magnetic layer or there is a vertical component in that direction, and the first and the second in-plane currents are logical input currents while the third in-plane current is used to control the implementation mode of the spin logic device.