Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A method for cartesian (IQ) to polar phase conversion includes: converting a first input value into a first absolute value, and a second input value into a second absolute value; converting the first absolute value into a first logarithmic value by calculating a scaled logarithmic value of the first absolute value, and the second absolute value into a second logarithmic value by calculating a scaled logarithmic value of the second absolute value; subtracting the first logarithmic value from the second logarithmic value, to provide a subtract value; and selecting a phase value from a plurality of phase values stored in a storage unit. Each of the plurality of phase values corresponds to a respective index value, and the phase value is selected taking the subtract value as the index value.

A computer performs generating, on the basis of mathematical expression information indicating a complex function, first display information on a first three-dimensional graph that indicates a relationship between a first variable indicating a real part of a first complex number input to the complex function indicated by the mathematical expression information, a second variable indicating an imaginary part of the first complex number, and a third variable indicating a real part of a second complex number output from the complex function, generating, on the basis of the mathematical expression information, second display information on a second three-dimensional graph that indicates a relationship between the first variable, the second variable, and a fourth variable indicating an imaginary part of the second complex number, and outputting display information including the first display information and the second display information.

Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.

A method of performing a quantum computation includes providing a quantum system comprising a plurality of qubits. The method includes encoding a computational problem into a problem Hamiltonian of the quantum system. The problem Hamiltonian is a single-body Hamiltonian comprising a plurality of adjustable parameters. The encoding includes determining, from the computational problem, a problem-encoding configuration for the plurality of adjustable parameters. The method includes performing N rounds of operations, wherein N≥2. Each round of the N rounds of operations includes determining a sequence of unitary operators, wherein each unitary operator in the sequence is a unitary operator being a unitary time evolution of the problem Hamiltonian, wherein the plurality of adjustable parameters of the problem Hamiltonian are in the problem-encoding configuration, or a unitary operator being a product of two or more short-range unitary operators. Each round of the N rounds of operations includes evolving the quantum system by applying the sequence of unitary operators to the quantum system. Each round of the N rounds of operations includes performing a measurement of one or more qubits of the quantum system. The method includes outputting a result of the quantum computation.

An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

Various embodiments are provided for conducting a power flow analysis using a set of line-wise power balance equations. In at least some embodiment, the set of line-wise power balance equations is solved using a Newton-Raphson technique. In various cases, the Jacobian matrix generated by the Newton-Raphson technique may directly indicate the transmission lines, or sets of transmission lines, which are most susceptible to voltage collapse. In at least one example application, the set of line-wise power balance equations may be used as equality constraints in an optimal power flow (OPF) formulation for solving an optimal power flow (OPF) problem.