Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

A data processing apparatus that converts a plurality of signed digits representing an input value in redundant representation comprises receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data from a previous iteration. Concatenation circuitry performs a concatenation of bits corresponding to the signed digit and bits of the previous intermediate data to produce updated intermediate data. Output circuitry provides the updated intermediate data as previous intermediate data of a next iteration. The previous intermediate data comprises S3[i] in non-redundant representation, which is at least part of the input value multiplied by 3 in non-redundant representation.

A method includes receiving a carry-sum value corresponding to a first portion of inputs to an adder, and receiving a second value corresponding to a second portion of inputs to the adder that do not overlap the first portion. Method includes providing an intermediate sum of carry and sum values of the carry-sum value, which generates a carry out (Cout). Method includes determining a sign of incremented second value, and a sign of non-incremented second value; complementing or passing, responsive to sign of incremented result, the incremented result as a first output; complementing or passing, responsive to sign of non-incremented result, the non-incremented result as a second output; complementing or passing, responsive to Cout, sign of incremented result, and sign of non-incremented result, the intermediate sum as a third output; selecting one of the first, second outputs responsive to Cout; and providing final sum comprising third output and selected output.

An information processing system according to an embodiment is configured to: acquire numerical representations and combination ratios for a plurality of component objects; acquire numerical representations for a plurality of reference objects; calculate a plurality of component feature vectors and a plurality of reference feature vectors by inputting the numerical representations of each of the plurality of component objects and the plurality of reference objects into a first machine learning model; calculate a probability vector for each of the plurality of component objects by inputting those feature vectors into a second machine learning model; and calculate a composite feature vector for a composite object obtained by combining the plurality of component objects, based on a plurality of probability vectors and a plurality of combination ratios.

An architecture is disclosed for an neural processing element having single instruction, multiple data (“SIMD”) compute lanes. The neural processing element includes compute lanes having multipliers configured to multiply a binary operand with another binary operand to generate a binary output. The neural processing element also includes a single adder tree for summing the binary outputs of the hardware binary multipliers. The neural processing element also includes a storage element for storing a binary output of the single hardware binary adder tree.

Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.

Method and device relate to the fields of deep learning and artificial intelligence; the method may include: acquiring N operand sets, N is a positive integer greater than one, the N operand sets are all in a first data input format or all in a second data input format, the first data input format includes half-precision floating point data and char data, and the second data input format includes signed fixed point data and the char data; determining input data corresponding to each operand, and inputting the input data into a corresponding multiplier to obtain an output result, where different operands correspond to different multipliers respectively; and calculating a sum of the output results of the multipliers by one or more adders to obtain an operation result of the N-dot-product operation.

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2.sup.ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−s.sub.y)}≤k≤(ew−1) where s.sub.y=1 for a signed floating point number and s.sub.y=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

A divider includes a digit recoder that recodes upper bits of a partial remainder into sets of lower-radix multiples without carry propagate addition. Elimination of the carry propagate adder makes computation of the quotient carry free and independent of the number of bits computed per cycle, thereby enabling a higher number of bits per cycle, as well as increased clock speeds.

A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.