Patent classifications
G06F7/49926
COMPUTATION APPARATUS, METHOD AND PROGRAM FOR THE SAME
A computation apparatus, a method of the same, and a program which perform a secure computation using fixed-point arithmetic, and overflow is unlikely to occur and the occurrence of division by zero can be detected when an odds ratio is calculated. The computation apparatus includes an odds ratio computation unit for obtaining an odds ratio between a first group (a+b) and a second group (c+d) based on four plaintext values a, b, c, and d, by means of secure computation; a zero-division detection unit for determining, by means of secure computation, whether or not at least one of the plaintext values b and c is not zero, and detecting division by zero; and a selection unit for selecting the odds ratio if division by zero is not detected, by means of secure computation.
Floating point instruction with selectable comparison attributes
An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.
MATRIX CALCULATION BLOCK AND COMPUTER-IMPLEMENTED METHOD FOR COMPUTER-AIDED GENERATION OF AN EXECUTABLE CONTROL PROGRAM
A matrix calculation block for a graphical modeling environment that executes block diagrams. Blocks of the block diagram have input ports and/or output ports, and are connectable through the respective ports by signal lines for data transmission. The matrix calculation block includes: at least one input port configured to receive an input matrix signal; a calculation definition having at least one error condition check; at least one output port configured for emitting an output signal, the output signal being a vector signal or a matrix signal; and an error port configured for emitting an error signal. A value of the error signal indicates an error state of a plurality of predefined error states, which includes an error-free state. The value of the error signal depends on whether the at least one error condition check is fulfilled or not.