A processor-implemented data processing method includes encoding a plurality of weights of a filter of a neural network using an inverted two's complement fixed-point format; generating weight data based on values of the encoded weights corresponding to same filter positions of a plurality of filters; and performing an operation on the weight data and input activation data using a bit-serial scheme to control when to perform an activation function with respect to the weight data and input activation data.

A method includes receiving a carry-sum value corresponding to a first portion of inputs to an adder, and receiving a second value corresponding to a second portion of inputs to the adder that do not overlap the first portion. Method includes providing an intermediate sum of carry and sum values of the carry-sum value, which generates a carry out (Cout). Method includes determining a sign of incremented second value, and a sign of non-incremented second value; complementing or passing, responsive to sign of incremented result, the incremented result as a first output; complementing or passing, responsive to sign of non-incremented result, the non-incremented result as a second output; complementing or passing, responsive to Cout, sign of incremented result, and sign of non-incremented result, the intermediate sum as a third output; selecting one of the first, second outputs responsive to Cout; and providing final sum comprising third output and selected output.

A method includes receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation. The upper shift circuit is configured to provide an upper output, the lower shift circuit is configured to provide a lower output, and the upper output concatenated with the lower output is a result of the arithmetic right shift operation. The method also includes receiving a shift value for the arithmetic right shift operation; responsive to the shift value, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output; and responsive to detecting the shift condition, providing, by a middle shift circuit, at least a portion of the operand to the lower shift circuit as a selectable input.

Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reducer can receive a particular input and generate multiple reduced inputs from the input. The reduced inputs can include reduced input data elements and/or a reduced weights. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide multiple reduced inputs with second shorter bit-length to the array. The systolic array may perform multiply-accumulate operations on each unique combination of the multiple reduced input data elements and the reduced weights to generate multiple partial outputs. The systolic array may sum the partial outputs to generate the output.

A method of quantization evaluation, including, receiving a floating point data set, determining a floating point neural network model output utilizing the floating point data set, quantizing the floating point data set utilizing a quantization model yielding a quantized data set, determining a quantized neural network model output utilizing the quantized data set, determining whether an accuracy error between the floating point neural network model output and the quantized neural network model output exceeds an predetermined error tolerance, determining a floating point neural network tensor output utilizing the floating point data set if the predetermined error tolerance is exceeded, determining a quantized neural network tensor output utilizing the quantized data set if the predetermined error tolerance is exceeded, determining a per-tensor error based on the floating point neural network tensor output and the quantized neural network tensor output and updating the quantization model based on the per-tensor error.

A processor determines an exponent common to a plurality of numerical values, determines a mantissa for each of the plurality of numerical values based on the determined exponent, and performs four arithmetic operations using a sign, the determined exponent, and the determined mantissa.

An arithmetic processing apparatus includes: a first determiner that determines, when a given learning model is repeatedly learned, an offset amount for correcting a decimal point position of fixed-point number data used in the learning in accordance with a degree of progress of the learning; and a second determiner that determines, based on the offset amount, the decimal point position of the fixed-point number data to be used in the learning. This configuration avoids lowering of the accuracy of a learning result of a learning model.

A compute-in-memory (CIM) macro device and an electronic device are proposed. The CIM macro device includes a CIM cell array including multiple CIM cells. First data is being divided into at least two bit groups including a first bit group which is the most significant bits of the first data and a second bit group which is the least significant bits of the first data, and the bit groups are respectively loaded in CIM cells of different columns of the CIM cell array. The electronic device includes at least one CIM macro and at least one processing circuit. The processing circuit is configured to receive and perform operation on parallel outputs respectively corresponding to the columns of the CIM cell array, where the parallel outputs include multiple correspondences, and where each of the correspondences includes most significant bits of an output activation and least significant bits of the output activation.

An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2.sup.N-1 single-level-cell (SLC) flash cells for each synapse (Y.sub.i) connected to a bit line forming a neuron. The method includes the step of providing an input vector (X.sub.i) for each synapse Y.sub.i wherein each input vector is translated into an equivalent electrical signal ES.sub.i (current I.sub.DACi, pulse T.sub.PULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 2.sup.0*ES.sub.i to (2.sup.N-1)*ES.sub.i. The method includes the step of providing a set of weight vectors or synapse (Y.sub.i), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Y.sub.i). The method includes the step of providing for 2.sup.N possible threshold voltage levels or resistance levels in the 2.sup.N-1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Y.sub.i into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Y.sub.i). The method includes the step of turning off all remaining 2.sup.N-1 flash cells of the respective synapse (Y.sub.i).

Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Y.sub.i) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.