A feedback apparatus and an FFT/IFFT processor. The apparatus comprises a radix-4 cascading operation module; radix-4 cascading operation module comprises: a twiddle factor generating unit, a complex multiplier, a delay switching unit, a butterfly operation unit, and an output switching unit; delay switching unit connects to the butterfly operation unit, complex multiplier, and output switching unit, respectively; and output switching unit connects to butterfly operation unit and delay switching unit. In present invention, on basis of the complex multiplier being fully utilized, and by using a dual-delay feedback structure circuit and designing a data delay buffer channel, the use efficiency of complex adders/subtractors is more effectively improved, the number of complex adders/subtractors required is evidently reduced, and circuit efficiency is significantly improved, thus effectively solving the problem in which radix-4SDF and radix-4SDC structures occupy a relatively large number of complex adders/subtractors.

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit x n-bit multiplications.

In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.