Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.

Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.

Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.