A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.

Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

A four-input lookup table (LUT4) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (LUT6) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.

A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.