A method includes receiving, by an x-bit adder, first and second addends. The x bits comprise a first portion and a second portion, the first portion is a power of two number of bits, and x is not a power of two. The method also includes computing a first sum of the first and second addends corresponding to the first portion. Computing the first sum provides a carry out bit. The method includes computing a non-incremented sum of the first and second addends corresponding to the second portion; computing an incremented sum of the first and second addends corresponding to the second portion; selecting one of the non-incremented sum and the incremented sum, responsive to the carry out bit, as a second sum; and providing a final sum by concatenating the second sum and the first sum.

A method includes receiving, by an x-bit adder, first and second addends. The x bits comprise a first portion and a second portion, the first portion is a power of two number of bits, and x is not a power of two. The method also includes computing a first sum of the first and second addends corresponding to the first portion. Computing the first sum provides a carry out bit. The method includes computing a non-incremented sum of the first and second addends corresponding to the second portion; computing an incremented sum of the first and second addends corresponding to the second portion; selecting one of the non-incremented sum and the incremented sum, responsive to the carry out bit, as a second sum; and providing a final sum by concatenating the second sum and the first sum.

A method includes receiving a carry-sum value corresponding to a first portion of inputs to an adder, and receiving a second value corresponding to a second portion of inputs to the adder that do not overlap the first portion. Method includes providing an intermediate sum of carry and sum values of the carry-sum value, which generates a carry out (Cout). Method includes determining a sign of incremented second value, and a sign of non-incremented second value; complementing or passing, responsive to sign of incremented result, the incremented result as a first output; complementing or passing, responsive to sign of non-incremented result, the non-incremented result as a second output; complementing or passing, responsive to Cout, sign of incremented result, and sign of non-incremented result, the intermediate sum as a third output; selecting one of the first, second outputs responsive to Cout; and providing final sum comprising third output and selected output.

A method includes receiving a carry-sum value corresponding to a first portion of inputs to an adder, and receiving a second value corresponding to a second portion of inputs to the adder that do not overlap the first portion. Method includes providing an intermediate sum of carry and sum values of the carry-sum value, which generates a carry out (Cout). Method includes determining a sign of incremented second value, and a sign of non-incremented second value; complementing or passing, responsive to sign of incremented result, the incremented result as a first output; complementing or passing, responsive to sign of non-incremented result, the non-incremented result as a second output; complementing or passing, responsive to Cout, sign of incremented result, and sign of non-incremented result, the intermediate sum as a third output; selecting one of the first, second outputs responsive to Cout; and providing final sum comprising third output and selected output.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.

One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.

An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.