Patent classifications
G06F7/535
TRUNCATED ARRAY FOR PERFORMING DIVISION
A computer-implemented method for deriving a hardware representation of a fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, includes normalising each of the plurality of divisors to form a plurality of multipliers; forming a summation array arranged to multiply the input x by any one of the plurality of multipliers; truncating the summation array by discarding all columns less significant than the k.sup.th column of the summation array below the position of a binary point, where k=[log.sub.2m]; determining a corrective constant in dependence on the maximum sum of the partial products discarded from the summation array for at least one of the multipliers; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant.
DIGIT-RECURRENCE SELECTION CONSTANTS
A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.
DIGIT-RECURRENCE SELECTION CONSTANTS
A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.
COMPUTATION APPARATUS, METHOD AND PROGRAM FOR THE SAME
A computation apparatus, a method of the same, and a program which perform a secure computation using fixed-point arithmetic, and overflow is unlikely to occur and the occurrence of division by zero can be detected when an odds ratio is calculated. The computation apparatus includes an odds ratio computation unit for obtaining an odds ratio between a first group (a+b) and a second group (c+d) based on four plaintext values a, b, c, and d, by means of secure computation; a zero-division detection unit for determining, by means of secure computation, whether or not at least one of the plaintext values b and c is not zero, and detecting division by zero; and a selection unit for selecting the odds ratio if division by zero is not detected, by means of secure computation.
COMPUTATION APPARATUS, METHOD AND PROGRAM FOR THE SAME
A computation apparatus, a method of the same, and a program which perform a secure computation using fixed-point arithmetic, and overflow is unlikely to occur and the occurrence of division by zero can be detected when an odds ratio is calculated. The computation apparatus includes an odds ratio computation unit for obtaining an odds ratio between a first group (a+b) and a second group (c+d) based on four plaintext values a, b, c, and d, by means of secure computation; a zero-division detection unit for determining, by means of secure computation, whether or not at least one of the plaintext values b and c is not zero, and detecting division by zero; and a selection unit for selecting the odds ratio if division by zero is not detected, by means of secure computation.
Neural net work processing
A neural network processor is disclosed that includes a combined convolution and pooling circuit that can perform both convolution and pooling operations. The circuit can perform a convolution operation by a multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and an add circuit accumulating the products determined by the multiply circuit in storage. The circuit can perform an average pooling operation by the add circuit accumulating input feature map data values in the storage, a divisor circuit determining a divisor value, and a division circuit dividing the data value accumulated in the storage by the determined divisor value. The circuit can perform a maximum pooling operation by a maximum circuit determining a maximum value of input feature map data values, and storing the determined maximum value in the storage.
Neural net work processing
A neural network processor is disclosed that includes a combined convolution and pooling circuit that can perform both convolution and pooling operations. The circuit can perform a convolution operation by a multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and an add circuit accumulating the products determined by the multiply circuit in storage. The circuit can perform an average pooling operation by the add circuit accumulating input feature map data values in the storage, a divisor circuit determining a divisor value, and a division circuit dividing the data value accumulated in the storage by the determined divisor value. The circuit can perform a maximum pooling operation by a maximum circuit determining a maximum value of input feature map data values, and storing the determined maximum value in the storage.
PROCESSING ELEMENT, NEURAL PROCESSING DEVICE INCLUDING SAME, AND MULTIPLICATION OPERATION METHOD USING SAME
The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.
PROCESSING ELEMENT, NEURAL PROCESSING DEVICE INCLUDING SAME, AND MULTIPLICATION OPERATION METHOD USING SAME
The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.
METHOD AND APPARATUS FOR CALCULATING DISTANCE BASED WEIGHTED AVERAGE FOR POINT CLOUD CODING
Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines to use a prediction mode for coding (encoding/decoding) information associated with a current point in a point cloud. In the prediction mode, the information associated with the current point is predicted based on one or more neighbor points of the current point. The processing circuitry calculates, using integer operations, a distance-based weighted average value based on distances of the one or more neighbor points to the current point, and determines the information associated with the current point based on the distance-based weighted average value.