Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

An encryption method and apparatus based on homomorphic encryption using a composition of functions. The encryption method includes generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on a composition of a function for a modulus corresponding to the ciphertext.

An encryption method and apparatus based on homomorphic encryption using a composition of functions. The encryption method includes generating a ciphertext by encrypting data, and bootstrapping the ciphertext by performing a modular reduction based on a composition of a function for a modulus corresponding to the ciphertext.

Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Homer methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Homer method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.

According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.

According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.

According to one embodiment, provided is a chip recognition system that recognizes a chip on a gaming table in an amusement place having the gaming table, the chip recognition system including: a game recording apparatus that records, as an image, a state of chips stacked on the gaming table, using a camera; an image analysis apparatus that performs an image analysis on the recorded image of the state of chips; a plurality of chip determination apparatuses including at least a first artificial intelligence apparatus that determines a number of the chips stacked, using an image analysis result obtained by the image analysis apparatus; and a second artificial intelligence apparatus that decides a correct number of the chips stacked, when the plurality of chip determination apparatuses obtain different determination results for the number of the chips stacked.