A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

A method and system for generating a high-order pseudo-random electromagnetic exploration signal. The method includes: constructing two or more basic unit signals according to an exploration requirement, where the basic unit signals are stairstep signals obtained by superposing a plurality of in-phase periodic square wave signals, and a frequency ratio between adjacent ones of the plurality of periodic square wave signals is 2; and superposing the two or more basic unit signals to obtain superposed stairstep signals, and correcting amplitudes to be consistent with amplitudes of the periodic square wave signals, to obtain high-order 2.sup.n sequence pseudo-random signals. The 2.sup.n sequence stairstep signals of different orders can be constructed within a limited frequency interval, improving the resolution during electromagnetic exploration.

A method and system for generating a high-order pseudo-random electromagnetic exploration signal. The method includes: constructing two or more basic unit signals according to an exploration requirement, where the basic unit signals are stairstep signals obtained by superposing a plurality of in-phase periodic square wave signals, and a frequency ratio between adjacent ones of the plurality of periodic square wave signals is 2; and superposing the two or more basic unit signals to obtain superposed stairstep signals, and correcting amplitudes to be consistent with amplitudes of the periodic square wave signals, to obtain high-order 2.sup.n sequence pseudo-random signals. The 2.sup.n sequence stairstep signals of different orders can be constructed within a limited frequency interval, improving the resolution during electromagnetic exploration.

A signal conversion circuit and a signal readout circuit are provided. The signal conversion circuit includes: an operational amplifier, configured to amplify an electric signal output by a sensing array; an input switched capacitor, wherein an end of the input switched capacitor is configured to receive the electric signal output by the sensing array, and another end of the input switched capacitor is coupled with an input end of the operational amplifier; and a feedback switched capacitor, wherein an end of the feedback switched capacitor is coupled with the input end of the operational amplifier, and another end of the feedback switched capacitor is coupled with an output end of the operational amplifier.

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F.sub.S/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.