A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Rate domain numerical processing comprises receiving an input serial data stream on a single input wire in which a multi-valued number is represented as a rate of pulse events comprising pulses, null pulses or a combination thereof. The rate of pulse events in an output serial data stream is varied in accordance with an operand to perform a multi-valued arithmetic operation selected from multiplication, division, addition and subtraction or a combination thereof. The rate may be varied by scaling the rate by an operand, which may be implemented using a count and compare circuit topology. The output serial data stream is output on a single output wire. The rate domain operations, specifically multiplication and division are accomplished without the resource & power intensive binary multiplier and binary divisions circuits. The operations are implemented using simple registers, adders, accumulators, counters, comparators, and basic logic, which is far more SWaP-C efficient.

The present invention relates to the technical field of printing in particular, to a frequency multiplication method and device, for solving the problem of poor quality of a printed image. One method comprises: for two adjacent pulse signals output from an encoder, determining a first kind of pulse signals and a second kind of pulse signals to be inserted between the two adjacent pulse signals according to a time interval between the two adjacent pulse signals and a frequency multiplication value corresponding to a longitudinal resolution; determining a period of the first kind of pulse signals to be inserted between the two adjacent pulse signals, and determining a period of the second kind of pulse signals to be inserted between the two adjacent pulse signals; and performing frequency multiplication processing on the two adjacent pulse signals. The embodiments of the invention further improve the printing quality of images.

A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.