An offload server includes: an application code analysis section configured to analyze source code of an application; a PLD processing designation section configured to identify loop statements of the application, generate a plurality of offload processing patterns designating, for each of the identified loop statements, parallel processing and/or pipeline processing on the PLD according to OpenCL, and perform compilation; an arithmetic intensity calculation section configured to calculate arithmetic intensities of the loop statements of the application; and a PLD processing pattern generation section configured to, on the basis of the arithmetic intensities calculated by the arithmetic intensity calculation section, narrow down the loop statements to, as candidates to be offloaded, those having an arithmetic intensity higher than a predetermined threshold.

A system configuration derivation device 90 includes a storage unit 91 that stores a concretization rule in which a method is specified for concretizing abstract configuration information by confirming an unconfirmed portion of the abstract configuration information, which is information indicating configuration of a system in which the unconfirmed portion is included, and a generation unit 92 that concretizes the abstract configuration information included in configuration requirements of the system using the concretization rule stored to generate system configuration information, which is information indicating the configuration of the system in which the unconfirmed portion is not included, on the basis of the configuration requirements.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

The present application is directed towards systems and methods for cluster-based code analysis and transformation. Cluster-based analysis may group code objects based on their similarity across functional areas, such as where a code object is cloned in multiple areas (e.g. sort functions that are duplicated across areas, or reports or tables that are identical). In some implementations, objects may be grouped into clusters by type, or based on reading from or writing to a common table. In some implementations, clustering at different layers may be possible.

When verifying rapidly the equivalence between source codes with respect to refactoring, the present invention performs two types of verification: verification based on structural comparison using structure graphs obtained by analyzing the source codes, and verification based on symbolic execution. If the structural comparison using the structure graphs can verify that the structures are identical with each other, then symbolic execution is not performed. Further, before the verification based on the structural comparison, the structure graphs of the source codes before and after refactoring are normalized on the basis of normalization information, which is defined for each refactoring pattern, and thereby adjusted so that the resulting structures are identical with each other when the refactoring is valid. Further, the structure graphs before and after the refactoring are subjected to abstraction before being subjected to symbolic execution for verification, thereby limiting locations to which symbolic execution is to be applied.

Provided are a module division assistance device, a module division assistance method, and a module division assistance program for automatically extracting a divisible module by utilizing information relating to a function used by a module. A keyword obtaining unit of an information processing device collects data relating to a function used by a module into keyword use data organized by modules, and a data analysis unit uses the data and a calculation method for an indivisibility calculation item specified by a user and stored in an indivisibility calculation item list, thereby calculating an indivisibility, and stores the indivisibility into indivisibility data. Then, with respect to a module to be subjected to division determination, a module division determination unit compares the indivisibility relating to a function relevant to the indivisibility calculation item specified by the user with a threshold value stored in the indivisibility calculation item list, thereby determining whether the module can be divided or not.

Herein disclosed is an optimization for a compiler, the optimization configured to assign numeric values, or semantic fingerprints, to portions of code, and to combine these fingerprints to arrive at fingerprints for larger and larger portions of code. The fingerprints can be provided to various consumers such as code redundancy optimization modules and copyright violation and malware/virus identification modules. The fingerprints can also be used to cluster similar code, and then code within each cluster can be merged. Merger can include creating a single merged portion of code including identical portions of code from the original portions of code and control flow and new arguments to account for differences between the original portions of code. The original portions of code can be replaced with wrappers that use new arguments to call to the merged portion of code.

The present application is directed towards systems and methods for providing a heat map interface for analyzing and reporting transformation capabilities of a source installation to a target installation of an application. Characteristics of the source installation are displayed in an easy, intuitive interface, providing improved efficiency in analysis and planning. Furthermore, the interface is interactive, allowing an administrator or user to select and apply transformation dispositions to code objects grouped into regions and sub-regions, providing versatility and accuracy of configuration.