Apparatuses, systems, and techniques to receive, by a processor of a computer system, one or more operations for a kernel; automatically generate, by the processor, one or more operators that perform the one or more operations on elements of one or more input data structures; and automatically generate, by the processor, the kernel that comprises the one or more operators.

A computerized technique for program simplification and specialization combines a partial interpretation of the program based on a subset of program functions to obtain variable states with concrete values at a program “neck.” These concrete values are then propagated as part of an optimization transformation that simplifies the program based on these constant values, for example, by eliminating branches that are never taken based on the constant values.

The present invention relates to a method of converting logic written in software code into text, comprising: converting the code to a structured format that represents the logic described in each function of said code as a tree of elements, and mapping the elements of the structured format into corresponding counterparts in a target language for obtaining a text translation of the structured format.

A method for compiling source code may include obtaining an abstract syntax tree (AST) node of an AST generated from the source code. The AST node may include a first value and a second value. The method may further include obtaining, for the AST node, an intermediate representation (IR) graph, determining that the first value is a constant, propagating the first value to the IR graph to obtain a first partially evaluated IR graph, and generating, for the AST node, a compiler. The first partially evaluated IR graph corresponds to a result of executing the compiler. The method may further include determining, by the compiler, that the second value is a constant, propagating, by the compiler, the second value to the first partially evaluated IR graph to obtain a second partially evaluated first IR graph, and executing the AST node using the second partially evaluated IR graph.

A processor circuit includes a compiler configured to receive a software program that comprises software code coded in an assembly language and inline software code coded in a high-level programming language, compile the inline software code coded in the high-level programming language within the software program into assembly code in the assembly language, and compile the assembly code and the software code coded in the assembly language into machine code for the processor circuit. A method includes determining if first and second instructions in a software program are combinable into one instruction word, combining the first and the second instructions in the software program into one instruction word if the first and the second instructions are combinable, and fetching the instruction word into a single register by storing the instruction word in the single register.

Provided ts an environment that can effectively supports development of a sequence program. A support device that supports the development of a sequence program deploys, when the sequence program is displayed, a call instruction of a unit program for configuring the sequence program to a circuit represented by a sequence logic defined by the unit program and displays the circuit, and changes, in accordance with an operation of changing the circuit, tire sequence logic of the circuit. When the sequence program is converted into executable code, the support device assigns, to the call instruction in the sequence program, either code of the sequence logic thus changed or code of the call instruction in accordance with a switching option.

Provided are methods and systems for inter-procedural optimization (IPO). A new IPO architecture (referred to as “ThinLTO”) is designed to address the weaknesses and limitations of existing IPO approaches, such as traditional Link Time Optimization (LTO) and Lightweight Inter-Procedural Optimization (LIPO), and become a new link-time-optimization standard. With ThinLTO, demand-driven and summary-based fine grain importing maximizes the potential of Cross-Module Optimization (CMO), which enables as much useful CMO as possible ThinLTO also provides for global indexing, which enables fast function importing; parallelizes some performance-critical but expensive inter-procedural analyses and transformations; utilizes demand-driven, lazy importing of debug information that minimizes memory consumption for the debug build; and allows easy integration of third-party distributed build systems. In addition, ThinLTO may also be implemented using an IPO server, thereby removing the need for the serial step.

An information processing apparatus includes a memory; and a processor coupled to the memory. The processor is configured to determine, when a first file among multiple files is compiled, whether a first function defined in the first file calls a second function that includes a loop process. The second function is defined in a second file among the files and different from the first file. The processor executes at least one of: duplicating the second function and a third function into the first file, when determining that the first function calls the second function and a call to the third function defined in any of the multiple files is present in the loop process; and duplicating the second function into the first file, when determining that the first function calls the second function and a pointer type dummy parameter of the second function is referred to within the loop process.

A complementary editor opens a plurality of views. Changes are received in a particular view of the plurality of views. The received changes are propagated to other views of the plurality of views other than the particular view and received by each particular view. The propagated changes are transformed in each particular view by a computer based on formatting constraints associated with each particular view and display of the transformed propagated changes is initiated in each particular view.

A memory stores code including a plurality of functions and a plurality of function calls each calling one of the plurality of functions. A processor calculates, for each of the plurality of functions, a plurality of index values including a first index value indicating an iteration status of a loop in the function and a second index value indicating the code size of the function. The processor calculates, for each of the plurality of function calls, an evaluation value based on the plurality of index values that are calculated for the function called by the function call. The processor selects one or more of the plurality of function calls, based on the evaluation value, and inlines the selected function calls.