The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Systems and methods analyze an executable simulation model to identify existing concurrency, determine opportunities for increasing concurrency, and develop proposed modifications for realizing the opportunities for increased concurrency. The systems and methods may label locations at the simulation model where concurrency exists, and provide information regarding the proposed modifications to increase the model's concurrency. The systems and methods may modify the simulation model if the additional concurrency is accepted. The systems and methods may operate within a higher-level programming language, and may develop the proposed modifications without lowering or translating the simulation model to a lower abstraction level. The systems and methods may also undo a modification, rolling the simulation model back to a prior design state. Accepting the proposed modifications may cause the simulation models to execute more efficiently, e.g., faster.

The exemplary embodiments are related to a pipeline manager configured to manage a software development pipeline. The pipeline manager receives, via a user interface (UI), a representation of a pipeline comprising a plurality of blocks, wherein each block comprises a defined input and a defined output, executes each block of the pipeline, validates output of each block of the pipeline based on the execution of the block and stores the output of each block and updating data that defines the pipeline based on the output of each block.

Controlling execution of application-specific hardware pipelines includes detecting, using computer hardware, a loop construct contained in a function within a design specified in a high-level programming language, extracting, using the computer hardware, the loop construct from the function into a newly generated function of the design, and generating, using the computer hardware, a state transition graph corresponding to the loop construct. The state transition graph can be pruned by relocating operations from the function entry state and the function exit state into the loop region. A circuit design defining, at least in part, a pipeline hardware architecture implementing the loop construct can be generated using the computer hardware based, at least in part, on the pruned state transition graph.

A software deployment method includes: analyzing a source code of an application; designating off-loadable processes of the application; performing a code conversion of the application according to a deployment destination environment; measuring the performance of the converted application on a verification device; making a setting for resource amounts according to the deployment destination environment; selecting a deployment place by calculating a deployment destination on the basis of a performance and a cost when the converted application is deployed while ensuring the resource amounts; performing, after deployment to an actual environment, a performance measurement test process to measure an actual performance of application; and performing, after performing the performance measurement test process, one or more of performing the code conversion, making the setting for resource amounts, selecting the deployment place, measuring the performance of the application on the verification device, and performing the performance measurement test process.

Systems and methods for version control of pipelined enterprise software are disclosed. Exemplary implementations may: store information for executable code of software applications that are installed and executable by users, receive first user input from a first user that represents selection by the first user of a first software pipeline for execution; receive second user input from a second user that represents a second selection by the second user of a second software pipeline for execution, wherein the second software pipeline includes different versions of software applications that are included in the first software pipeline; facilitate execution of the first software pipeline for the first user; and facilitate execution of the second software pipeline for the second user at the same time as the execution of the first software pipeline for the first user.

A method for a compilation, an electronic device and a readable storage medium are provided. The method for a compilation includes analyzing source program data to determine a target irregular branch, generating an update data flow graph according to the target irregular branch, and mapping the update data flow graph to a target hardware to complete the compilation.

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.

An apparatus stores a program including a description of loop processing of iterating a plurality of instructions, and rearranges an execution sequence of the plurality of instructions in the program such that the loop processing is pipelined by software pipeline. The apparatus inserts an instruction to use a register for single instruction multiple data (SIMD) extension instruction, into the description of the loop processing in the program.

System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first data flow program portion is iterative. Program code implementing a plurality of second data flow program portions is automatically generated based on the first data flow program portion, where each of the second data flow program portions is configured to execute a respective one or more iterations. The plurality of second data flow program portions are configured to execute at least a portion of iterations concurrently during execution of the data flow program. Execution of the plurality of second data flow program portions is functionally equivalent to sequential execution of the iterations of the first data flow program portion.