Patent classifications
G06F8/447
Two-Phase Application Development Device
A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.
Multi-chip compatible compiling method and device
A multi-chip compatible compiling method includes: extracting common characteristic information of Makefiles; configuring variable attribute information of the Makefiles; obtaining a universal Makefile template for multiple chips according to the common characteristic information and the variable attribute information of the Makefiles; traversing a project to be compiled in the universal Makefile template by a compilation module, recording path information of a dependency file of the project to be compiled, replacing a variable value in the universal Makefile template, and determining automation configuration information of the universal Makefile template; invoking an incremental compilation mechanism of a Make tool according to the automation configuration information of the universal Makefile template to obtain a target Makefile of the project to be compiled; and processing the target Makefile by rule information and pseudo-target tag information in the Makefiles to obtain an executable file generated by compilation.
Mixed mode programming
A mixed mode programming method permitting users to program with graphical coding blocks and textual code within the same programming tool. The mixed mode preserves the advantages of graphical block programming while introducing textual coding as needed for instructional reasons and/or for functional reasons. Converting a graphical code block or group of blocks to a textual block lets the user see a portion of the textual code in the context of a larger program. Within one programming tool the mixed mode method allows users to learn programming and build purely graphical blocks; then transition into mixed graphical and textual code and ultimately lead to their ability to program in purely textual code. The mixed mode further allows users to program using any combination of drag-and-drop graphical blocks and typed textual code in various forms.
MULTI-CHIP COMPATIBLE COMPILING METHOD AND DEVICE
A multi-chip compatible compiling method includes: extracting common characteristic information of Makefiles; configuring variable attribute information of the Makefiles; obtaining a universal Makefile template for multiple chips according to the common characteristic information and the variable attribute information of the Makefiles (S130); traversing a project to be compiled in the universal Makefile template by a compilation module, recording path information of a dependency file of the project to be compiled, replacing a first variable value in the universal Makefile template, and determining automation configuration information of the universal Makefile template (S140); invoking an incremental compilation mechanism of a Make tool according to the automation configuration information of the universal Makefile template to obtain a target Makefile of the project to be compiled (S150); and processing the target Makefile by rule information and pseudo-target tag information in the Makefiles to obtain an executable file generated by compilation (S160).
METHOD AND SYSTEM FOR GENERATING AN AUTOMATION ENGINEERING PROJECT IN A TECHNICAL INSTALLATION USING MULTIDISCIPLINARY APPROACH
A method and system for generating an automation engineering project in a technical installation is provided. The method includes receiving, by a processing unit, a request to generate an automation engineering project for a technical installation. The method further includes generating a first name graph based on the information about the hardware configuration associated with the automation engineering project. The method further includes generating, by the processing unit, a second name graph based on the analysis of the one or more modifications of the hardware configuration of the technical installation. The method further includes generating, by the processing unit, the automation engineering project from the plurality of engineering objects based on a comparison of the first name graph and the second name graph.
SOFTWARE AND HARDWARE COLLABORATIVE COMPILATION PROCESSING SYSTEM AND METHOD
A software and hardware collaborative compilation processing method and system. The system comprises an environment configurator, a command parser, a code filler, a scheduler and a heterogeneous target system, wherein the code filler is configured for obtaining the source program path of a user, reading source codes and identifying the heterogeneous target system according to a macro definition, complementing the codes related to the heterogeneous target system, carrying out primary filling and secondary filling on the source codes; the scheduler is configured for realizing compilation scheduling and execution scheduling functions respectively; the heterogeneous target system is configured for compiling and processing user modal data, and comprises at least two heterogeneous target subsystems; each target subsystem comprises a target-related middle-end compiler, a back-end compiler and a target-related running environment.
System of Heterogeneous Reconfigurable Processors for the Data-Parallel Execution of Applications
A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.
Link-time driver polymorphism for embedded systems
Specific images of an OS are built using only the driver bindings that are necessary to link the OS to the particular hardware of a client device. A device tree of the client device is analyzed to identify the hardware components. Databases of different hardware source code for various hardware drivers are maintained and used to craft the driver bindings and instances for the hardware of the client device. The device tree is also analyzed to identify compatibility strings of the various hardware on the client device. The hardware source code is searched for these compatibility strings to see if a driver exists in the databases of hardware source code. Specific driver bindings and driver instances with the actual variable names and configuration parameters of the identified hardware drivers are then generated and included in an image of the OS that may be installed on the client device.
SYSTEM AND METHOD OF USING SUSTAINABILITY TO ESTABLISH COMPILATION METHODS ALIGNED WITH SUSTAINABILITY GOALS
Generating compilation methods using sustainability. Code is compiled in a manner that accounts for sustainability values. When a compilation request is received, sustainability values are identified. The resources needed to fulfill the compilation request are identified based on the sustainability values and available resources. Once the resources that are likely to best meet the sustainability values, the compilation request is performed using those resources.
DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETEROGENEOUS COMPUTING
An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.