A semiconductor device includes three integrated circuits. One of the integrated circuits includes: a first connector configured to connect to a device; and a transmitter. The transmitter is configured to transmit to another integrated circuit, first data on each of a plurality of pieces of packet data. The transmitter is also configured to, when the first connector is connected to the device, while a second controller is performing a second process, transmit, to a first controller, a request to process data transmitted from the device.

A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

A data loading circuit and method are provided. The circuit is configured to load data for a feature map calculated by a neural network into a calculation circuit, wherein the size of the convolution kernel of the neural network is K*K data, and a window corresponding to the convolution kernel slides with a step size of S in the feature map, where K and S are positive integers and S<K, the circuit comprising: two data loaders comprising a first data loader and a second data loader; and a controller configured to: control the first data loader to be in a data outputting mode and control the second data loader to be in a data reading mode, when the window slides within K consecutive rows of the feature map.

A method, system and apparatus for providing bound information accesses in buffer protection, including providing one-to-one mapping between a general-purpose register and bound information in a BI (bound information) register, saving loaded bound information in the BI register for future use, providing integrity of the bound information in the BI register that is maintained along program execution, and providing a pro-active load of the bound information with one-bit extra control on load instruction of the BI register.

Systems, apparatuses, and methods for managing a number of wavefronts permitted to concurrently execute in a processing system. An apparatus includes a register file with a plurality of registers and a plurality of compute units configured to execute wavefronts. A control unit of the apparatus is configured to allow a first number of wavefronts to execute concurrently on the plurality of compute units. The control unit is configured to allow no more than a second number of wavefronts to execute concurrently on the plurality of compute units, wherein the second number is less than the first number, in response to detection that thrashing of the register file is above a threshold. The control unit is configured to detect said thrashing based at least in part on a number of registers in use by executing wavefronts that spill to memory

Systems and methods are directed to a device comprising a product status synchronization device. Examples of the product status synchronization device comprise a plurality of input ports and an encoder input, each of the input ports coupled to one of a plurality of registers and configured to receive a signal indicative of a status assigned to a product by one of a plurality of process stations, and to register the status assigned to the product into the one of the plurality of registers coupled to the input port, wherein one or more of the plurality of process stations are located at different distances from a predetermined location along a processing line and are configured to asynchronously process one or more products moving through the processing line.

Aspects of the subject disclosure are directed towards safely projecting a diffracted light pattern, such as in an infrared laser-based projection/illumination system. Non-diffracted (zero-order) light is refracted once to diffuse (defocus) the non-diffracted light to an eye safe level. Diffracted (non-zero-order) light is aberrated twice, e.g., once as part of diffraction by a diffracting optical element encoded with a Fresnel lens (which does not aberrate the non-diffracted light), and another time to cancel out the other aberration; the two aberrations may occur in either order. Various alternatives include upstream and downstream positioning of the diffracting optical element relative to a refractive optical element, and/or refraction via positive and negative lenses.

A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

A system for facilitating efficient hardware-firmware interactions may include (i) a plurality of memory registers, (ii) a hardware module that directly reads from and writes to the plurality of memory registers and is configured to interpret a special marker that distinguishes between register write operations and non-register-write operations, and (iii) a firmware module that directs the hardware module to perform operations at least in part by sending the special marker. Various other methods, systems, and computer-readable media are also disclosed.

A system and method for the storage, within one or more virtual execution context registers, tracing information indicative of process/code flow within a processor system. This stored information can include a time stamp, information indicative of where the instruction pointer of the system was pointing prior to any process discontinuity, information indicative of where the instruction pointer of the system was pointing after any process discontinuity, and the number of times a specific instruction or sub-process is executed during a particular process. The data collected and stored can be utilized within such a system for the identification and analysis of processing hot-spots.