Patent classifications
G06F9/4418
Method and apparatus for waking up device, electronic device, and storage medium
A method and apparatus for waking up a device, an electronic device, and a storage medium are provided, which are related to fields of image processing and deep learning. The method includes: acquiring an environment image of a surrounding environment of a target device in real time, and recognizing a face region of a user in the environment image; acquiring a plurality of facial landmarks in the face region, and acquiring a left eye image and a right eye image according to the facial landmarks; acquiring a left eye sight classification result and a right eye sight classification result according to the left eye image and the right eye image; and waking up the target device in a case of determining that the user is looking at the target device according to the left eye sight classification result and the right eye sight classification result.
Digital device for performing booting process and control method therefor
The present specification discloses a digital device for performing a hibernation booting process and a control method therefor. Here, the digital device according to an embodiment of the present invention comprises: a first memory; a second memory storing a snapshot image generated on the basis of pieces of page data of the first memory; and a control unit for generating the snapshot image, wherein the control unit primarily deduplicates duplicated page data in the first memory and selectively secondarily deduplicates duplicated page data by comparing the duplicated page data with the snapshot image prestored in the second memory, wherein data fragmentation is minimized through the secondary deduplication step.
Subsystem for configuration, security, and management of an adaptive system
An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
Controlling operational state of an electronic apparatus based on user proximity and user input
An electronic apparatus includes processing unit configured to execute system processing, an object detection unit configured to detect an object present within a predetermined detection range, and an operation control unit configured to control the system processing according to a detection state detected by the object detection unit to make a transition to one of a first operating state and a second operating state in which at least part of the system processing is more limited than that in the first operating state. When a transition from the first operating state to the second operating state is made regardless of the detection state detected by the object detection unit, where the operation control unit prohibits the transition to the first operating state according to the detection state detected by the object detection unit.
Hypervisor hibernation
Upon receiving a request to hibernate a hypervisor of a virtualization system running on a first computer, acts are carried out to capture a state of the hypervisor, where the state of the hypervisor comprises hypervisor logical resource parameters and an execution state of the hypervisor. After hibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor into a data structure, the data structure is moved to a different location. At a later moment in time, the data structure is loaded onto a second computing machine and restored. The restore operation restores the hypervisor and all of its state, including all of the virtual machines of the hypervisor as well as all of the virtual disks and other virtual devices of the virtual machines. Differences between the first computing machine and the second computing machine are reconciled before execution of the hypervisor on the second machine.
Methods, controllers, and machine-readable storage media for automated commissioning of equipment
Tools and techniques are described to automate commissioning of physical spaces. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. Controllers also have access to databases of the physical space such that they can check that sensors in the space record the correct information for device activity, and sensors can cross-check each other for consistency. Once a physical space is commissioned, incentives can be sought based on commissioning results.
Methods and apparatus for boot time reduction in a processor and programmable logic device environment
Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.
POWER CONTROL CIRCUITRY FOR CONTROLLING POWER DOMAINS
A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.
INTERCONNECT WAKE RESPONSE CIRCUIT AND METHOD
In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.
CHIPSET RECONFIGURATION BASED ON DEVICE DETECTION
Example implementations relate to chipset reconfiguration based on device detection. For example, a method includes detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system, and reconfiguring a chipset of the computing system based on the detected storage device. The method also includes performing a power cycle on chipset standby power to trigger a chipset configuration reload.