The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

A system and method of scheduling timer access includes a first physical processor with a first physical timer executing a first guest virtual machine. A hypervisor determines an interrupt time remaining before an interrupt is scheduled and determines the interrupt time is greater than a threshold time. Responsive to determining that the interrupt time is greater than the threshold time, the hypervisor designates a second physical processor as a control processor with a control timer and sends, to the second physical processor, an interval time, which is a specific time duration. The hypervisor grants, to the first guest virtual machine, access to the first physical timer. The second physical processor detects that the interval time expires. Responsive to detecting that the interval time expired, an inter-processor interrupt is sent from the second physical processor to the first physical processor, triggering the first guest virtual machine to exit to the hypervisor.

A processor of a sensor device performs measurement processing by one or a plurality of sensors and transmission processing of sensor data generated by the measurement processing. The sensor device includes a processing routine table that stores a processing routine configured to include, corresponding to an identifier for identifying processing performed by a processor, a type of the processing, an execution trigger of the processing, and trigger information that prescribes a trigger for transmitting the sensor data. The processor controls processing in a processing routine of the processing routine table, based on trigger information, so that the sensor data subjected to measurement processing is immediately transmitted, or temporarily stored in a buffer and transmitted after a predetermined time.

An information processing apparatus that uses a graphical processing unit (GPU) for inference processing, the information processing apparatus includes a processor. The processor configured to monitor a message output from an application that executes the inference processing. The processor configured to determine, from a pattern of the message, timing of a start and an end of core processing that uses the GPU, the core processing serving as a core of the inference processing. The processor configured to start the core processing when there is no process executing another core processing and accumulates a process identifier that identifies a process of the core processing in a queue when there is a process executing the another core processing in a case where the timing of the start of the core processing is determined.

Techniques are disclosed for providing method for providing an event timer for event synchronization across Kubernetes clusters. The event timer is configured to provide event synchronization on behalf of microservice instances in the cloud computing environment. In response to a request for an event timer for a timed event, it is determined whether the requested event timer has been started for a second microservice instance. If the requested event timer has been started, a state of the requested event timer is sent to the first microservice instance If the requested event timer has not been started, the requested event timer is instantiated, and a state of the instantiated event timer is stored in a database. The instantiated event timer is independent of the first and second microservice instances. In response to an expiration of the event timer, a single callback for processing of the event is generated.

Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.

C-state transitions due to software timer interrupts can be minimized. A timer interrupt synchronizer can be deployed on a computing device to function as an intermediary between software components that rely on timer interrupts and a timer interrupt architecture of the computing device. When the software components request timer interrupts, the timer interrupt synchronizer can ensure that timer interrupts having the same frequency can be synchronized to occur at the same time. As a result of this synchronization, a CPU can experience fewer C-state transitions due to the timer interrupts.

Techniques for supporting invocations of the RDTSC (Read Time-Stamp Counter) instruction, or equivalents thereof, by guest program code running within a virtual machine (VM), including guest program code running within a secure hardware enclave of the VM, are provided. In one set of embodiments, a hypervisor can activate time virtualization heuristics for the VM, where the time virtualization heuristics cause accelerated delivery of system clock timer interrupts to a guest operating system (OS) of the VM. The hypervisor can further determine a scaling factor to be applied to timestamps generated by one or more physical CPUs, where the timestamps are generated in response to invocations of a CPU instruction made by guest program code running within the VM, and where the scaling factor is based on the activated time virtualization heuristics. The hypervisor can then program the scaling factor into the one or more physical CPUs.

An improved real-time operating system (RTOS) design that uses cycle-based scheduling rather than tick-based scheduling is described herein. Using cycle-based scheduling, versus the traditional tick-based scheduling, provides technical benefits to embedded systems. For example, the cycle-based scheduling can change the basic unit of time of the embedded system by increasing the resolution of scheduling. Instead of relying on the system tick used in typical RTOS implementations (e.g., a tick that occurs every 1 millisecond), the improved RTOS design described herein uses CPU cycles internally for some or all operations. Operations such as task delays, timeouts, and/or software timers, which were specified in units of system ticks in typical RTOS implementations, can now be specified in CPU cycles.

In the present invention, when an abnormality occurs in a task, regardless of whether a critical section is being executed, timeout detection is realized by determining whether the critical section (CS) is necessary for the design in a preset task execution time and a certain period of time to distinguish between necessary interrupt disable and abnormal interrupt disable. A vehicle control device includes task execution means for causing a system to execute a task, and interrupt processing means for performing an interrupt process at the time of execution of the task. A maskable interrupt and a non-maskable interrupt that is commanded to execute after the maskable interrupt are included, the maskable interrupt is commanded to execute during an interrupt disable time, and then the non-maskable interrupt is executed.