A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.

A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.

A waveform conversion unit (42) of a numerically controlled oscillator has a cosine table (101) and a sine table (102) in which parameters for cosine wave and sine wave signal generation are stored, a correction mechanism (50) for generating correction values according to the phase of an inputted phase signal, an adder (111) for generating a cosine wave signal from a parameter in the cosine table (101) and a correction value, and an adder (112) for generating a sine wave signal from a parameter in the sine table (102) and a correction value. The correction mechanism (50) uses waveform data which is a kind of parabolic data and whose phase interval is more minute than the phase interval of the parameters in each table (101), (102) to generate correction values for correcting cosine wave and sine wave signals to be found by linear interpolation.

A waveform conversion unit (42) of a numerically controlled oscillator has a cosine table (101) and a sine table (102) in which parameters for cosine wave and sine wave signal generation are stored, a correction mechanism (50) for generating correction values according to the phase of an inputted phase signal, an adder (111) for generating a cosine wave signal from a parameter in the cosine table (101) and a correction value, and an adder (112) for generating a sine wave signal from a parameter in the sine table (102) and a correction value. The correction mechanism (50) uses waveform data which is a kind of parabolic data and whose phase interval is more minute than the phase interval of the parameters in each table (101), (102) to generate correction values for correcting cosine wave and sine wave signals to be found by linear interpolation.

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

The analog multiplier includes a first signal input module, and a second signal input module or a third signal input module. The first signal input module is configured to output a frequency modulation signal. The second signal input module includes a first energy storage unit, a first switch unit, and a second switch unit. The first switch unit and the second switch unit are alternately turned on or turned off based on a frequency of the frequency modulation signal. The third signal input module includes a second energy storage unit, two third switch units, and two fourth switch units. The third switch unit and the fourth switch unit are alternately turned on or turned off based on the frequency of the frequency modulation signal.

The analog multiplier includes a first signal input module, and a second signal input module or a third signal input module. The first signal input module is configured to output a frequency modulation signal. The second signal input module includes a first energy storage unit, a first switch unit, and a second switch unit. The first switch unit and the second switch unit are alternately turned on or turned off based on a frequency of the frequency modulation signal. The third signal input module includes a second energy storage unit, two third switch units, and two fourth switch units. The third switch unit and the fourth switch unit are alternately turned on or turned off based on the frequency of the frequency modulation signal.

An electronic circuit includes word lines; bit lines intersecting the word lines at a plurality of grid points; and resistive processing units located at the grid points. Baseline stochastic pulse input units are coupled to the word lines; differential stochastic pulse input units are coupled to the word lines; and bitline stochastic pulse input units are coupled to the bit lines. Control circuitry coupled to the pulse input units is configured to cause each of the baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from the base input data, and each of the bitline stochastic pulse input units to generate a bitline pulse train using bit line input data. Neural network weights can thus be stored in the resistive processing units.